FIN210AC Datasheet, PDF (6/17 Pages) Fairchild Semiconductor – 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz

Clock Pass-Through Mode
Clock pass-through mode allows a harmonic rich clock source to be sent to the serializer in a CTL format to reduce the
overall harmonic content of the phone, and can reduce the need for EMI filters. The Master Clock Pass through mode
performs a translation to the clock in the CTL link, and does not serialize this signal. The following describes how to enable
this functionality for an image sensor (See Figure 6).
Deserializer Configuration (DIRI=0)
1. Connect CKREF(BGA pin A6) to GROUND
2. Connect master clock to STROBE (BGA pin B5)
Serializer Configuration (DIRI=1)
1. CKSI passes master clock to CKP output (BGA pin C1)
CKREF and STROBE Signals
Please note that there is a setup and hold time between STROBE and data that must be met as seen on the electrical
characteristics section. The relationship between CKREF and STROBE can be synchronous or asynchronous depending on
what is available in the system. It is suggested that if the signals are synchronous and in normal operation that CKREF is tied
to STROBE as close to the chip as possible. If you are running an asynchronous or spread spectrum setup, please be aware
this may result on cycle jitter on the CKP signal. They cycle jitter does not effect the output data and clock relationship, the
display or end application should continue to work as normal.
PLL Note
Please note that the PLL ranges can overlap, power consumption can be reduced by selecting the operation in the lower end
of the higher speed PLL range.
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
6
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