FIN210AC Datasheet, PDF (3/17 Pages) Fairchild Semiconductor – 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz

FIN210AC (Deserializer DIRI=0) Pin Descriptions
Pin Name
Description
DIRI
XTERM
S0
Control to determine serializer or deserializer configuration.
Control to determine if using internal or external termination
Signals used to define the edge rate of parallel I/O.
0 Deserializer
1 Serializer
0 Internal termination used
1 External termination required on CKSI & DSI
See Table 2 Deserializer (DIRI=0) Control Pin.
S1
Signals used to define the edge rate of parallel I/O.
See Table 2 Deserializer (DIRI=0) Control Pin.
PWS0
Configure CKP pulse width.
See Table 2 Deserializer (DIRI=0) Control Pin.
PWS1
Configure CKP pulse width.
See Table 2 Deserializer (DIRI=0) Control Pin.
/ENZ
DP[1:10]
CKP
DSI+
DSI-
CKSI+
CKSI-
CKSO+
CKSO-
CKREF
STROBE
/DIRO
VDDP
VDDS
VDDA
GND
N/C
High-Z or known state outputs during power down
See Table 5 Deserializer (DIRI=0) Control Pin.
LV-CMOS parallel data output. (N/C if not used)
LV-CMOS word clock output or Pixel clock output.
CTL Differential serial input data signals.
DSI+: Positive signal; DSI-: Negative signal.
CTL Differential deserializer input bit clock.
CKSI+: Positive signal; CKSI-: Negative signal.
CTL Differential serializer output bit clock.
CKSO+: Positive signal; CKSO-: Negative signal.
No connect unless in “clock pass-through” mode.
LV-CMOS clock input and PLL reference.
No connect unless in “clock pass-through” mode.
LV-CMOS strobe input for latching data into the serializer.
No connect unless in “clock pass-through” mode.
LV-CMOS Output. Inversion of DIRI in normal operation.
No connect if not used.
Power supply for parallel I/O. (All VDDP pins must be connected to VDDP)
Power supply for serial I/O.
Power supply for core.
All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 28, 29, GND PAD must be grounded.
No connect. BGA: G1, F2; MLP: 10, 11; (Do not connect to GND or VDD)
Note:
2. 0=GND; 1=VDDP
FIN210AC (Deserializer DIRI=0) Pin Configurations
1
2
3
4
5
6
A ^DP[4]
DP[2]
XTRM
/ENZ
N/C
CKREF
B ^DP[6]
DP[5]
DP[1]
N/C STROBE /DIRO
C ^CKP
N/C
DP[3]
N/C
CKSO+ CKSO-
D ^N/C
DP[7]
VDDP
GND
DSI+
DSI-
E ^DP[8]
DP[9]
GND
VDDS CKSI+ CKSI-
F ^DP[10]
N/C
N/C
VDDA
N/C
DIRI
DP[4] 1
DP[5] 2
DP[6] 3
VDDP 4
CKP 5
DP[7] 6
DP[8] 7
DP[9] 8
DESERIALIZER
GND PAD
24 CKSO+
23 CKSO-
22 DSI-
21 DSI+
20 CKSI-
19 CKSI+
18 DIRI
17 VDDS
G ^N/C
N/C
PWS1 PWS0
S1
S0
42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View)
32-pin MLP, 5mm x 5mm, .5mm pitch (Top View)
(Center pad must be grounded)
Figure 3. FIN210AC (Deserializer DIRI=0) Pin Assignments (Top View)
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
3
www.fairchildsemi.com