FIN210AC Datasheet, PDF (2/17 Pages) Fairchild Semiconductor – 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz

FIN210AC (Serializer DIRI=1) Pin Descriptions
Pin Name
Description
DIRI
CTL_ADJ
Control to determine serializer or deserializer configuration.
Adjusts CTL drive to compensate for environmental conditions
and length.
0 Deserializer
1 Serializer
0 Low drive (low power)
1 High drive (high power)
S0
Configure frequency range for the PLL.
See Table 1 Serializer (DIRI=1) Control Pin.
S1
Configure frequency range for the PLL.
See Table 1 Serializer (DIRI=1) Control Pin.
PLL0
Divide or adjust the serial frequency.
See Table 1 Serializer (DIRI=1) Control Pin.
PLL1
CKREF
STROBE
DP[1:10]
CKSO+
CKSO-
DSO+
DSO-
CKSI+
CKSI-
CKP
/DIRO
VDDP
VDDS
VDDA
GND
N/C
Divide or adjust the serial frequency.
See Table 1 Serializer (DIRI=1) Control Pin.
LV-CMOS clock input and PLL reference.
LV-CMOS strobe input for latching data (DP [1:12]) into the serializer on the rising edge.
LV-CMOS parallel data input. (GND input if not used)
CTL Differential serializer output bit clock.
CKSO+: Positive signal; CKSO-: Negative signal.
CTL Differential serial output data signals.
DSO+: Positive signal; DSO-: Negative signal.
CTL Differential deserializer input bit clock.
CKSI+: Positive signal; CKSI-: Negative signal.
No connect unless in “clock pass-through” mode.
LV-CMOS word clock output or Pixel clock output.
No connect unless in “clock pass-through” mode.
LV-CMOS output, Inversion of DIRI in normal operation. Can be used to drive the DIRI
signal of the deserializer where the interface needs to be turned around.
No connect if not used.
Power supply for parallel I/O. (All VDDP pins must be connected to VDDP)
Power supply for serial I/O.
Power supply for core.
All GND pins must be connected to ground. BGA: all GND pads. MLP: Pin 29 & GND PAD must be grounded.
No connect. (Do not connect to GND or VDD)
Note:
1. 0=GND; 1=VDDP
FIN210AC (Serializer DIRI=1) Pin Configurations
1
2
3
4
5
6
A ^DP[4]
DP[2]
GND CTL_ADJ
N/C
CKREF
B ^DP[6]
DP[5]
DP[1]
N/C
STROBE /DIRO
C CKP
N/C
DP[3]
N/C
CKSO+ CKSO-
D ^N/C
DP[7]
VDD P
GND
DSO -
DSO+
E ^DP[8]
DP[9]
GND
VDD S
CKS I+
CKSI -
F ^DP[10]
GND
N/C
VDD A
N/C
DIRI
DP[4] 1
DP[5] 2
DP[6] 3
VDDP 4
CKP 5
DP[7] 6
DP[8] 7
DP[9] 8
SERIALIZER
GND PAD
24 CKSO+
23 CKSO-
22 DSO+
21 DSO-
20 CKSI-
19 CKSI+
18 DIRI
17 VDDS
G ^GND
N/C
PLL 1
P LL 0
S1
S0
42-Ball BGA, 3.5 x 4.5mm, .5mm pitch (Top View)
32-pin MLP, 5 x 5mm, .5mm pitch (Top View)
(Center pad must be grounded)
Figure 2. FIN210AC (Serializer DIRI=1) Pin Assignments (Top View)
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
2
www.fairchildsemi.com