FIN210AC Datasheet, PDF (5/17 Pages) Fairchild Semiconductor – 10-Bit Serializer / Deserializer Supporting Cameras and Small Displays up to 48MHz

Table 3. Deserializer S0 & S1 Control Pins (Note: All edge rates are typical values)
Slow Edge Rates
LVCMOS Output Edge Rates
~7 - 8ns (CL = 8pF)
S0
S1
0
1
Medium Edge Rates
~4 - 5ns (CL = 8pF)
1
1
Fast Edge Rates
~2 - 3ns (CL = 8pF)
1
0
Power Down
0
0
Pulse Width Calculations
CKP Pulse Width Low Time=(PLL Multiplier • Pwidth Multiplier) / (CKREF•12)
(1)
Example: CKREF=26MHz; PLL Multiplier=1; Pwidth Multiplier=6
CKP Pulse width=(1 • 6) / (26MHz • 12)=19.2ns
(2)
CKREF = Strobe 50% Duty Cycle
If CKREF = Strobe the below control states will provide a ~ 50% duty cycle pulse width output on CKP
Table 4. CKREF = Strobe 50% Duty Cycle
PLL0
1
Serializer
PLL1
0
PWS0
0
Deserializer
PWS1
0
Power-Down States
When both S1 and S0 signals are 0, regardless of the state of the DIRI signal, the FIN210AC resets and powers down. The
power-down mode shuts down all internal analog circuitry, disables the serial input and output of the device, and resets all
internal digital logic. Table 5 indicates the state of the input states and output buffers in Power-Down mode.
Table 5. Power-Down
Signal Pins
DP[1:10]
CKP
STROBE
CKREF
/DIRO
DIRI=1 (Serializer)
Inputs Disabled
HIGH
Input Disabled
Input Disabled
0
DIRI=0 (Deserializer)
/ENZ = 0
Outputs High-Z
High-Z
Input Disabled
Input Disabled
1
DIRI=0 (Deserializer)
/ENZ = 1
Outputs Low
High
Input Disabled
Input Disabled
1
© 2009 Fairchild Semiconductor Corporation
FIN210AC • Rev. 1.0.1
5
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