FAN5033 Datasheet, PDF (4/39 Pages) Fairchild Semiconductor – 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller

Pin #
14
15
16
17 to 19
20 to 22
23
24 to 31
32
-
Name
GND
OD
NC
SW3 to
SW1
PWM3 to
PWM1
VCC
VID7 to
VID0
VIDSEL
Exposed
Paddle
Description
Ground. All internal biasing and logic output signals of the device are referenced to this
ground.
Output Disable. This pin is actively pulled low when the EN input is low or when V_CC is
below its UVLO threshold to disable the external MOSFET drivers. (Also referred to as
OD# in the text of this document.)
No Connection. This pin is not connected internally.
Switching Node Current Balance Inputs. Sense the switching side of the inductor and
used to measure the current level in each phase. The SW pins of unused phases should
be left open.
PWM Outputs. Each output is connected to the input of an external MOSFET driver,
such as the FAN5109. Connecting the PWM3 output to VCC disables that phase,
allowing the FAN5033 to operate as a two-phase controller.
Supply Voltage for the Device.
Voltage Identification Code Inputs. These digital inputs are connected to the internal
DAC and used to program the output voltage. These pins have 1µA internal pull-down;
so if they are left open, the input state is decoded as logic low.
VID Table Select Input. A logic low selects the extended VR10 DAC table and a logic
high selects the VR11 DAC table. This pin has a 1µA internal pull-down; so if left open,
the input state is decoded as logic low.
Internally connected to die ground. May be connected to ground or left floating.
Connect to ground for lowest package thermal resistance.
© 2006 Fairchild Semiconductor 2006
FAN5033 Rev. 1.0.0
4 of 39
www.fairchildsemi.com