FAN5033 Datasheet, PDF(18/39 Page) Fairchild Semiconductor – 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller

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FAN5033 Datasheet, PDF (18/39 Pages) Fairchild Semiconductor – 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller

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outside of the specified range, if the VID DAC inputs are

in no CPU mode, or whenever the EN pin is pulled low.

PWRGD is blanked during a VID OTF event for a period

of ~200Âµs to prevent false signals during the time the

output is changing.

The PWRGD circuitry also incorporates an initial turn-on

delay time (TD5) based on the DELAY timer. Prior to the

SS voltage reaching the programmed VID DAC voltage

of -100mV, the PWRGD pin is held low. Once the SS

pin is within 100mV of the programmed DAC voltage,

the capacitor on the DELAY pin begins to charge up. A

comparator monitors the DELAY voltage and enables

PWRGD when the voltage reaches 1.7V. The PWRGD

delay time is therefore set by a current of 15ÂµA charging

a capacitor from 0V to 1.7V.

OUTPUT CROWBAR

As part of the protection for the load and output

components of the supply, the PWM outputs are driven

low (turning on the low-side MOSFETs) when the output

voltage exceeds the upper crowbar threshold. This

crowbar action stops once the output voltage falls below

the release threshold of approximately 300mV.

Turning on the low-side MOSFETs pulls down the

output as the reverse current builds up in the inductors.

If the output over-voltage is due to a short in the high-

side MOSFET, this action current-limits the input supply,

protecting the microprocessor.

OUTPUT ENABLE AND UVLO

For the FAN5033 to begin switching, the input supply

(VCC) to the controller must be higher than the UVLO

threshold and the EN pin must be higher than its 0.85V

threshold. This initiates a system start-up sequence. If

either UVLO or EN is less than their respective

thresholds, the FAN5033 is disabled, which holds the

PWM outputs low, discharges the DELAY and SS

capacitors, and forces PWRGD and OD# signals low.

In the application circuit, the OD# pin should be

connected to the OD# inputs of the FAN5009 or

FAN5109 drivers. Pulling OD# low disables the drivers

such that both DRVH and DRVL are driven low. This

turns off the bottom MOSFETs to prevent them from

discharging the output capacitors through the output

inductors. If the bottom MOSFETs were left on, the

output capacitors could ring with the output inductors

and produce a negative output voltage to the processor.

NTC Resistance versus Temperature

Normalized to 25C

1.0

0.8

0.6

0.4

0.2

0.0

100

125

Temperature (C)

Figure 11: Typical NTC Resistance vs. Temperature

FAN5033 Rev. 1.0.0

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