FAN5033 Datasheet, PDF (17/39 Pages) Fairchild Semiconductor – 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller

the inrush current during start-up. The soft-start time
depends on the value of the boot voltage and C_SS.
Once the SS voltage is within 100mV of the boot
voltage, the boot voltage delay time (TD3) is started.
The end of the boot voltage delay time signals the
beginning of the second soft-start time (TD4). The SS
voltage changes from the boot voltage to the
programmed VID DAC voltage (either higher or lower)
using the SS amplifier with the limited output current of
15µA. The voltage of the FB pin follows the ramping
voltage of the SS pin, limiting the inrush current during
the transition from the boot voltage to the final DAC
voltage. The second soft-start time depends on the boot
voltage, the programmed VID DAC voltage, and C_SS.
If either EN is taken low or V_CC drops below UVLO,
DELAY and SS are reset to ground to be ready for
another soft-start cycle. Figure 9 shows typical start-up
waveforms for the FAN5033.
starts the latch-off timer. Because the controller
continues to operate during the latch-off delay time, if
the OC is removed before the 1.7V threshold is
reached, the controller returns to normal operation and
the DELAY capacitor is reset to GND.
The latch-off function can be reset by cycling the supply
voltage to the FAN5033 or by toggling the EN pin low for
a short time. To disable the short-circuit latch-off
function, an external resistor can be placed in parallel
with C_DLY to prevent the DELAY capacitor from charging
up to the 1.7V threshold. The addition of this resistor
causes a slight increase in the delay times.
During start-up, when the output voltage is below
200mV, a secondary current limit is active. This
secondary current limit clamps the internal COMP
voltage at the PWM comparators to 1.5V. Typical over-
current latch-off waveforms are shown in Figure 10.
Vcore
Vcore
V_VRREADY
V_DELAY
V_OD#
V_EN
V_DELAY
V_PHASE1
Figure 9: Start-up Waveforms
CURRENT LIMIT, SHORT-CIRCUIT. AND LATCH-OFF
PROTECTION
The FAN5033 compares a programmable current limit
set point to the voltage from the output of the current
sense amplifier. The current limit level is set with the
resistor from the ILIMIT pin to ground. During operation,
the voltage on ILIMIT is 1.7V. The current through the
external resistor is internally scaled to give a current
limit threshold of 10mV/µA. If the voltage between
CSREF and CSCOMP rises above the current limit
threshold, the internal current limit amplifier controls the
internal COMP voltage to maintain the average output
current at the limit.
After TD5 has completed, an over-current (OC) event
starts a latch-off delay timer. The delay timer uses the
DELAY pin timing capacitor. During current limit, the
DELAY pin current is reduced to 3.75 µA. When the
voltage on the delay pin reaches 1.7V, the controller
shuts down and latches off. The current limit latch-off
delay time is therefore set by the current of 3.75µA
charging the delay capacitor 1.7V. This delay is four
times longer than the delay time during the start-up
sequence. If there is a current limit during start-up, the
FAN5033 goes through TD1 to TD5 in current limit and
Figure 10: Over-Current Latch-off Waveforms
DYNAMIC VID
The FAN5033 has the ability to dynamically change the
VID inputs while the controller is running. This allows
the output voltage to change while the supply is running
and supplying current to the load. This is commonly
referred to as VID on-the-fly (OTF). A VID OTF can
occur under either light or heavy load conditions. The
processor signals the controller by changing the VID
inputs in multiple steps from the start code to the finish
code. This change can be positive or negative.
When a VID input changes state, the FAN5033 detects
the change and ignores the DAC inputs for a minimum
of 200ns. This time prevents a false code due to logic
skew while the eight VID inputs are changing.
Additionally, the first VID change initiates the PWRGD
and CROWBAR blanking functions for a minimum of
100µs to prevent a false PWRGD or CROWBAR event.
Each VID change resets the internal timer.
POWER GOOD MONITORING
The power good comparator monitors the output voltage
via the CSREF pin. The PWRGD pin is an open-drain
output whose high level (when connected to a pull-up
resistor) indicates that the output voltage is within the
nominal limits specified based on the VID voltage
setting. PWRGD goes low if the output voltage is
© 2006 Fairchild Semiconductor 2006
FAN5033 Rev. 1.0.0
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