FAN5033 Datasheet, PDF (16/39 Pages) Fairchild Semiconductor – 8-Bit Programmable, 2- to 3-Phase, Synchronous Buck Controller

lowest cost, or output inductor DCR sensing with a
thermistor, for improved accuracy with tracking of
inductor temperature.
To measure the differential voltage across the output
inductors, the positive input of the CSA (CSREF pin) is
connected, using equal value resistors, to the output
capacitor side of the inductors. The negative input of the
CSA (CSSUM pin) is connected, again using equal value
resistors, to the MOSFET side of the inductors. The
CSA’s output (CSCOMP) is a voltage equal to the voltage
dropped across the inductors, times the gain of the CSA,
and is inversely proportional to the output current.
The gain of the CSA is set by connecting an external
feedback resistor between the CSA’s CSCOMP and
CSSUM pins. A capacitor, connected across the
resistor, is used to create a low pass filter to remove
high-frequency switching effects and to create a RC
pole to cancel the zero created by the L/DCR of the
inductor. The end result is that the voltage between the
CSCOMP and CSREF pins is inversely proportional to
the output current (CSCOMP goes negative relative to
CSREF as current increases) and the CSA gain sets the
ratio of the CSA output voltage change as a function of
output current change. This voltage difference is used
by the current limit comparator and is also used by the
droop amplifier to create the output load line.
The CSA is designed to have a low offset input voltage.
The sensing gain is determined by external resistors so
that it can be extremely accurate.
LOAD LINE IMPEDANCE CONTROL
The FAN5033 has an internal “Droop Amp” that
effectively subtracts the voltage applied between the
CSCOMP and CSREF pins from the FB pin voltage of
the error amplifier, allowing the output voltage to be
varied independent of the DAC setting. A positive
voltage on CSCOMP (relative to CSREF) increases the
output voltage and a negative voltage decreases it.
Since the voltage between the CSA’s CSCOMP and
CSREF pins is inversely proportional to the output,
current causes the output voltage to decrease an
amount directly proportional to the increase in output,
current, creating a droop or “Load Line.” The ratio of
output voltage decrease to output current increase is the
effective R_o of the power supply and is set by the DC
gain of the CSA.
CURRENT CONTROL MODE AND THERMAL
BALANCE
The FAN5033 has individual SW inputs for each phase.
They are used to measure the voltage drop across the
bottom FETs to determine the current in each phase.
This information is combined with an internal ramp to
create a current balancing feedback system. This gives
good current balance accuracy that takes into account,
not only the current, but also the thermal balance
between the bottom FETs in each phase.
External resistors R_SW1 through R_SW3 can be placed in
series with individual SW inputs to create an intentional
current imbalance if desired, such as in cases where
one phase has better cooling and can support higher
currents. It is best to have the ability to add these
resistors in the initial design to ensure that placeholders
are provided in the layout. To increase the current in a
phase, increase R_SW for that phase. Even adding a
resistor of a few hundred ohms can make a noticeable
increase in current, so use small steps.
The amplitude of the internal ramp is set by a resistor
connected between the input voltage and the RAMPADJ
pin. This method also implements the Voltage Feed
Forward function.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The FAN5033 uses differential sensing in conjunction
with a high accuracy DAC and a low offset error
amplifier to maintain a worst-case specification of
±7.7mV differential sensing accuracy over its specified
operating range.
A high gain-bandwidth error amplifier is used for the
voltage control loop. The voltage on the FB pin is
compared to the DAC voltage to control the output
voltage. The FB voltage is also effectively offset by the
CSA output voltage for accurately positioning the output
voltage as a function of current. The output of the error
amplifier is the COMP pin, which is compared to the
internal PWM ramps to create the PWM pulse widths.
The negative input (FB) is tied to the output sense
location with a resistor (R_B) and is used for sensing and
controlling the output voltage at this point. Additionally a
current source is connected internally to the FB pin,
which causes a fixed DC current to flow through R_B.
This current creates a fixed voltage drop (offset voltage)
across R_B. The offset voltage adds to the sensed output
voltage, which causes the error amp to regulate the
actual output voltage lower than the programmed VID
voltage by this amount. The main loop compensation is
incorporated into the feedback by an external network
connected between FB and COMP.
DELAY TIMER
The delay times for the start-up timing sequence are set
with a capacitor from the DELAY pin to ground, as
described in the Start-Up Sequence section. In UVLO or
when EN is logic low, the DELAY pin is held at ground.
Once the UVLO and EN are asserted, a 15µA current
flows out of the DELAY pin to charge C_DLY. A
comparator, with a threshold of 1.7V, monitors the
DELAY pin voltage. The delay time is therefore set by
the 15µA charging the delay capacitor from 0V to 1.7V.
This DELAY pin is used for multiple delay timings (TD1,
TD3, and TD5) during start-up. DELAY is also used for
timing the current limit latch off as explained in the
CURRENT LIMIT section.
SOFT-START
The soft-start times for the output voltage are set with a
capacitor from the SS pin to ground. After TD1 and the
phase-detection cycle have been completed, the SS
time (TD2 in Figure 8) starts. The SS pin is
disconnected from GND and the capacitor is charged up
to the 1.1V boot voltage by the SS amplifier, which has
a limited output current of 15µA. The voltage at the FB
pin follows the ramping voltage on the SS pin, limiting
© 2006 Fairchild Semiconductor 2006
FAN5033 Rev. 1.0.0
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