XRT73R12_07 Datasheet, PDF (80/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
TABLE 38: XRT73R12 REGISTER MAP SHOWING CHANNEL CONTROL REGISTERS (CC_N)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n STS-1/DS3_n SR/DR_n
R/W
R/W
R/W
R/W
R/W
R/W
TABLE 39: CHANNEL CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM6
(N = [0:11] & M= 0-5 & 8-D)
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-6
Reserved
5
PRBS Enable
R/W PRBS Generator and Receiver Enable - Channel_n:
This READ/WRITE bit-field is used to enable or disable the PRBS Generator
and Receiver within a given Channel of the XRT73R12.
If the user enables the PRBS Generator and Receiver, then the following will
happen.
1. The PRBS Generator (which resides within the Transmit Section of
the Channel) will begin to generate an unframed, 2^15-1 PRBS
Pattern (for DS3 and STS-1 applications) and an unframed, 2^23-1
PRBS Pattern (for E3 applications).
2. The PRBS Receiver (which resides within the Receive Section of the
Channel) will now be enabled and will begin to search the incoming
data for the above-mentioned PRBS patterns.
0 - Disables both the PRBS Generator and PRBS Receiver within the corre-
sponding channel.
1 - Enables both the PRBS Generator and PRBS Receiver within the corre-
sponding channel.
NOTES:
1. To check and monitor PRBS Bit Errors, DR (Dual Rail) mode will be
over-ridden and Single Rail mode forced for the duration of this
mode. This will configure the RNEG/LCV_n output pin to function
as a PRBS Error Indicator. All errors will be flagged on this pin.
The errors will also be accumulated in the 16 bit Error counter for
the channel.
2. If the user enables the PRBS Generator and PRBS Receiver, the
Channel will ignore the data that is being accepted from the
System-side Equipment (via the TxPOS_n and TxNEG_n input
pins) and will overwrite this outbound data with the PRBS Pattern.
3. The system must provide an accurate and stable data-rate clock to
the TxClk_n pin during this operation.
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