XRT73R12_07 Datasheet, PDF (64/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
FIGURE 37. CHANNEL LEVEL INTERRUPT ENABLE REGISTER - CR96 (ADDRESS LOCATION = 0X60)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Reserved
Reserved
Channel 5
Interrupt
Enable
Channel 4
Interrupt
Enable
Channel 3
Interrupt
Enable
Channel 2
Interrupt
Enable
Channel 1
Interrupt
Enable
R/W
R/W
R/W
R/W
R/W
BIT 0
Channel 0
Interrupt
Enable
R/W
BIT
NUMBER
7,6
5
4
3
2
1
0
NAME
Unused
Channel 5 Interrupt Enable
Channel 4 Interrupt Enable
Channel 3 Interrupt Enable
Channel 2 Interrupt Enable
Channel 1 Interrupt Enable
Channel 0 Interrupt Enable
TYPE
DESCRIPTION
R/W Channel n Interrupt Enable Bit:
This READ/WRITE bit is used to:
• To enable Channel n for Interrupt Generation at the Channel
Level
• To disable all Interrupts associated with Channel n within the
XRT73R12
This is a "master" enable bit for each channel. This bit allows
control on a per channel basis to signal the Host of selected error
conditions.
If a bit is cleared, no interrupts from that channel will be sent to the
Host via the INT.
If the bit is set (logic 1), any generated interrupt in channel n that
has been enabled in the Interrupt Enable register (IERn) for the
channel will activate the INT pin to the Host.
0 - Disables all Channel n related Interrupts.
1 - Enables Channel n-related Interrupts. The user must enable
individual Channel n related Interrupts at the source level, before
they are can generate an interrupt.
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