XRT73R12_07 Datasheet, PDF (50/89 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT

XRT73R12
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.2
7.2 ASYNCHRONOUS AND SYNCHRONOUS DESCRIPTION
Whether the LIU is configured for Asynchronous or Synchronous mode, the following descriptions apply. The
synchronous mode requires an input clock (PCLK) to be used as the microprocessor timing reference. Read
and Write operations are described below.
Read Cycle (For Pmode = "0" or "1")
Whenever the local µP wishes to read the contents of a register, it should do the following.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the µP and
the LIU microprocessor interface block.
3. Next, the µP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action enables the bi-directional data bus output drivers of the LIU.
4. After the µP toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inform the µP that the data is available to be read by the µP, and that it is ready for the next command.
5. After the µP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
6. The CS input pin must be pulled "High" before a new command can be issued.
Write Cycle (For Pmode = "0" or "1")
Whenever a local µP wishes to write a byte or word of data into a register within the LIU, it should do the follow-
ing.
1. Place the address of the target register on the address bus input pins Addr[7:0].
2. While the µP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables communication between the µP and
the LIU microprocessor interface block.
3. The µP should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus D[7:0].
4. Next, the µP should indicate that this current bus cycle is a Write operation by toggling the WR input pin
"Low". This action enables the bi-directional data bus input drivers of the LIU.
5. After the µP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
to inform the µP that the data has been written into the internal register location, and that it is ready for the
next command.
6. The CS input pin must be pulled "High" before a new command can be issued.
FIGURE 35. ASYNCHRONOUS µP INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS
Addr[7:0]
CS
D[7:0]
RD
WR
RDY
READ OPERATION
t₀
Valid Address
WRITE OPERATION
t₀
Valid Address
Valid Data for Readback
t₁
t₂
Data Available to Write Into the LIU
t₃
t₄
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