XRS10L120 Datasheet, PDF (8/52 Pages) Exar Corporation – SERIAL ATA II: 1:2 PORT MULTIPLIER

XRS10L120
PRELIMINARY
SERIAL ATA II: 1:2 PORT MULTIPLIER
REV. P1.0.1
2.0 FUNCTIONAL DESCRIPTION
A top-level view of the XRS10L120 is shown in Figure 3 outlining the interfaces to the device and the required
support components. The data path can be seen at the top of the device. This includes the output transmit and
input receive path at the top left, providing the upstream interface to the host, and the output transmit and input
receive paths at the top right, providing the downstream interface to the target devices. The clocking, control,
and configuration interfaces are shown below the dashed line.
FIGURE 3. XRS10L120 INTERFACES
Serial ATA Upstream
Interface to HBAs
SiT_P0/SiT_N0 SOT_P/N[1:0]
SiR_P0/SiR_N0 SOR_P/N[1:0]
Output Port Status LED
Control and
configuration
Interface
DRACT[1:0]
HBACT0
RESETB
PWRDNB
MDC
MDIO¹
VDDA
RBIAS
Calibration Resistor
49.9 Ω ± 1%
CMU_REF_P/N
XOD
XOG
TCK
TDI
TDO¹
TMS
TRST
Serial ATA Downstream
Interface to HBAs
Reference Clock
Crystal Oscillator Inputs
JTAG Interface
The XRS10L120 incorporates identical instantiations of a dual-channel Serial ATA II 3 Gbps PHY macro. This
common building block provides a uniform implementation with common characteristics and a common
register map, but provides a functional implementation of independent PHY blocks. Digital logic
implementations of Serial ATA link layer blocks along with port multiplier logic provide the remainder of the data
path within the XRS10L120. In addition, management and control interfaces including an MDIO interface for
register control, a JTAG interface for boundary scan purposes, and a resistor calibration circuit complete the
device. A block diagram of the XRS10L120 is shown in Figure 4.
FIGURE 4. XRS10L120 BLOCK DIAGRAM
SIR
SATA II
SIT
3G PHY
SATA II
LINK
LAYER
RATE
ADJUST
FIFO
SATA II
LINK
LAYER
PORT
MULTIPLIER
SATA II
LINK
LAYER
SATA II
3G PHY
SATA II
3G PHY
SOT 0
SOR 0
SOT 1
SOR 1
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