XRS10L120 Datasheet, PDF (24/52 Pages) Exar Corporation – SERIAL ATA II: 1:2 PORT MULTIPLIER

XRS10L120
PRELIMINARY
SERIAL ATA II: 1:2 PORT MULTIPLIER
REV. P1.0.1
4.2 Macro Registers
The registers outlined in this section are common to each of the three Serial ATA dual PHY macros as
described in the previous section. As such, each listed register is present in each of the 1, 2, and 3 MDIO
register spaces, and will perform the stated function on the specified Serial ATA lane.
The registers within each dual PHY macro are split into three sections:
Transmit/receive lane 0 registers:
Address range 000*****
Transmit/receive lane 1 registers:
Address range 001*****
PLL registers:
Address range 010*****
Bias generator registers:
Address range 011*****
ADDRESS
HEX
N.0000
N.0021
TABLE 9: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1 AND 2)
BIT(S)
NAME
R/W
DEFAULT
DESCRPTION
7:6
Reserved
RO
5:4
Receive_Test0[1:0]
R/W
5:4
Receive_Test1[1:0]
3:2
Transmit_Test0[1:0] R/W
3:2
Transmit_Test1[1:0]
1
selFourFive
R/W
0
SATAPCIEXB[
R/W
-
Reserved
00 PRBS checker control
00 = disable PRBS checkers
01 = enable 2^23-1 checkers
10 = enable 2^31-1 checkers
11 = enable 2^10-1 checkers
00 Test Pattern Control
00 = Use input data from DATAIN
01 = Generate 2^23-1 PRBS
10 = Generate 2^31-1 PRBS
11 = Generate 2^10-1 PRBS
1
0 = Output data is x8
1 = Output data is x10
1
Tx output swing booster bit
0 = boost swing by 10%
1 = nominal swing
22