XRS10L120 Datasheet, PDF (14/52 Pages) Exar Corporation – SERIAL ATA II: 1:2 PORT MULTIPLIER

XRS10L120
PRELIMINARY
SERIAL ATA II: 1:2 PORT MULTIPLIER
REV. P1.0.1
2.7 Test and Loopback Modes
The XRS10L120 provides for loopback testing on both the host and device interfaces, and incorporates a
number of internal testing features, as outlined in the following subsections.
2.7.1 Host Side Loopback Modes
The XRS10L120 supports two forms of host loopback modes: a shallow serial loopback implemented within
the host PHY macro, or a deep parallel loopback implemented within the device PHY macros after the port
selector and port multiplier functionality.
SHALLOW HOST LOOPBACK MODE
The shallow host loopback mode is shown in Figure 10. In this mode, the incoming data stream from the host
and embedded clock are recovered by an internal CDR, and the deserialized data is retransmitted serially back
to the host, as clocked by the recovered clock. In this implementation, the received data is still transmitted to
the internal port selector block and will propagate through to the device side output pins.
FIGURE 10. SHALLOW HOST LOOPBACK MODE
SiT
SOT0
SOR0
SiR
PHY Layer
Dual PHY
SOT1
SOR1
Port Multiplier
DEEP HOST LOOPBACK MODE
The deep host loopback mode is shown in Figure 11. In this mode, the incoming data stream from the host is
transmitted through the digital blocks within the XRS10L120, and the loopback path is implemented at the
device-side Serial ATA PHY block. Note that once again, the looped back data is still transmitted on the device-
side output pins. The deep host loopback mode is enabled by using the Parallel Loopback registers for the
downstream PHYs in Device 2 or 3. This received data must be in the form of valid SATA frames for a deep
loopback to be successful, or the internal logic must be bypassed via MDIO register settings.
FIGURE 11. DEEP HOST LOOPBACK MODE
SiT
SOT0
SOR0
SiR
PHY Layer
Dual PHY
SOT1
SOR1
Port Multiplier
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