XRS10L120 Datasheet, PDF (27/52 Pages) Exar Corporation – SERIAL ATA II: 1:2 PORT MULTIPLIER

REV. P1.0.1
ADDRESS
HEX
N.000D
N.002D
N.000E
N.002E
N.000F
N.002F
N.0010
N.0030
N.0011
N.0031
N.0012
N.0032
PRELIMINARY
XRS10L120
SERIAL ATA II: 1:2 PORT MULTIPLIER
TABLE 9: TRANSMIT/RECEIVE LANE REGISTERS (MDIO DEVICE 1 AND 2)
BIT(S)
NAME
R/W
DEFAULT
DESCRPTION
7:6
Reserved
RO
7:6
5:0
MaxWakeWidth0
RW
5:0
MaxWakeWidth1
7:6
Reserved
RO
5:0 MinWakeWidth0[5:0] RW
MinWakeWidth1[5:0]
7:6
Reserved
RO
5:0 MaxWakeWidth0[5:0]
MaxWakeWidth1[5:0]
7:6
Reserved
RO
5:3
rcvRef0[2:0]
RW
rcvRef1[2:0]
2:0
squelchdivsel[2:0]
7:0
rcvdetdelay0[10:0]
(lower 8 bits)
7:3
Reserved
RO
2:0
rcvdetdelay0[10:0]
(upper 3 bits)
-
Reserved
010110 Upper bound count of idle for COMINIT/COM-
RESET
-
Reserved
000100 Lower bound count of idle for COMWAKE
-
Reserved
000111 Upper bound count of idle for COMWAKE
-
Reserved
011 Percent of full swing that TX must reach during
Receiver Detect to count as receiver present
(not applicable to SATA PHY macros)
010 Value by which to divide squelch clock
000 = divide by 1
001 = divide by 2
010 = divide by 4
011 = divide by 6
100 = divide by 8
101 = divide by 10
110 = divide by 12
111 = divide by 14
Number of SYSCLK cycles to wait between
assertion of RECDET and clocking comparator
-
Reserved
Number of SYSCLK cycles to wait between
assertion of RECDET and clocking comparator
for receiver detect (not applicable to SATA PHY
macros)
25