XRS10L120 Datasheet, PDF (33/52 Pages) Exar Corporation – SERIAL ATA II: 1:2 PORT MULTIPLIER

REV. P1.0.1
PRELIMINARY
XRS10L120
SERIAL ATA II: 1:2 PORT MULTIPLIER
TABLE 10: PLL CONFIGURATION/DEBUG REGISTERS (MDIO DEVICE 1 AND 2)
ADDRESS
HEX
BIT(S)
NAME
R/W
DEFAULT
DESCRIPTION
N.0047
7:3
Reserved
RO
-
Reserved
2
tdccovrd
0 1 = use tdccen bits to activate/disable transmit duty
cycle correction ports
0 = use pwrdnTxB bits to activate/disable transmit
duty cycle correction ports
1:0
tdccen[1:0]
00 When tdccovrd is asserted, tdccen[N] enables/dis-
ables duty cycle correction from transmit lane N.
1 = enable duty cycle correction from lane N
0 = disable duty cycle correction from lane N
N.0048
7:1
Reserved
RO
-
Reserved
0
pllClkDiv5en
1 1 = enable pllclkDiv5 0 = disable pllClkDiv5
TABLE 11: BIAS GENERATOR CONFIGURATION/DEBUG REGISTERS (MDIO DEVICE 1 AND 2)
ADDRESS
HEX
BIT(S)
NAME
RW RESET VALUE
DESCRIPTION
N.0060 7:3
Reserved
Reserved
1
bgPwrdn
0
Powers down core of bandgap circuit
0 = Normal operation
1 = power down core of bandgap
The bandgap voltage can be overdriven externally by
setting both bgTesten and bgPwrdn
0
bgTestEn
0
Bandgap test mode enable
0 = Normal operation
1 = Connect bandgap voltage to bgMuxOut
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