XR17V352 Datasheet, PDF (8/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
PRELIMINARY
HIGH PERFORMANCE DUAL PCI EXPRESS UART
REV. P1.0.1
1.0 XR17V352 INTERNAL REGISTERS
The XR17V352 UART register set is very similar to the previous generation PCI UARTs. This makes the V352
software compatible with the previous generation PCI UARTs. Minimal changes are needed to the software
driver of an existing Exar PCI UART driver so that it can be used with the V352 PCIe UART.
There are three different sets of registers as shown in Figure 3. The PCI Local Bus Configuration Space
Registers is needed for plug-and-play auto-configuration. This auto-configuration feature makes installation
very easy into a PCI system and it is part of the PCI local bus specification. The second register set is the
Device Configuration Registers that are also accessible directly from the PCI bus for programming general
operating conditions of the device and monitoring the status of various functions common to both channels.
These functions include both channel UARTs’ interrupt control and status, 16-bit general purpose timer control
and status, multipurpose inputs/outputs control and status, sleep mode, soft-reset, and device identification
and revision. And lastly, each UART channel has its own set of internal UART Configuration Registers for its
own operation control and status reporting. Both sets of channel registers are embedded inside the device
configuration registers space, which provides faster access. The second and third set of registers are mapped
into 2K of the PCI bus memory address space. The following paragraphs describe all 3 sets of registers in
detail.
FIGURE 3. THE XR17V352 REGISTER SETS
Device Configuration and
UART[1:0] Configuration
Registers are mapped on
to the Base Address
Register (BAR) in a 2K-
byte of memory address
space
PCIe
Interface
PCI Local Bus
Configuration Space
Registers for Plug-
and-Play Auto
Configuration
Vendor and Sub-vendor ID
and Product Model Number
in External EEPROM
Channel 0 16550 compatible
registers + enhanced registers
Device Configuration Registers
Channel 0 TX FIFO, RX FIFO,
RX FIFO + Status Burst Reg
Channel 1 16550 compatible
registers + enhanced registers
Device Configuration Registers
0x0000
0x0080
0x0100
0x0400
Channel 1 TX FIFO, RX FIFO,
RX FIFO + Status Burst Reg
0x07FF
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device is read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, located at an address offset of
0x10 in the configuration space. Custom modification of certain registers is possible by using an external
93C46 EEPROM. The EEPROM contains the device vendor and sub-vendor data, along with 6 other words of
information (see “Section 1.2, EEPROM Interface” on page 12) required by the auto-configuration setup.
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