XR17V352 Datasheet, PDF (51/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

PRELIMINARY
XR17V352
REV. P1.0.1
HIGH PERFORMANCE DUAL PCI EXPRESS UART
MCR[7]: Clock Prescaler Select (requires EFR bit [4]=1)
• Logic 0 = Divide by one. The internal 125MHz clock is fed directly to the Programmable Baud Rate
Generator without further modification, i.e., divide by one (default).
• Logic 1 = Divide by four. The prescaler divides the internal 125MHz clock by 4 and feeds it to the
Programmable Baud Rate Generator, hence, data rates become one forth.
MCR[6]: Infrared Encoder/Decoder Enable (requires EFR bit [4]=1)
The state of this bit depends on the sampled logic level of pin ENIR during power up, following a hardware
reset (rising edge of RST# input). Afterward user can override this bit for desired operation.
• Logic 0 = Enable the standard modem receive and transmit character interface.
• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. While in this mode, the TX/RX output/
input are routed to the infrared encoder/decoder. The data input and output levels will conform to the IrDA
infrared interface requirement. As such, while in this mode the infrared TX output will be a LOW during idle
data conditions. FCTR bit [4] may be selected to invert the RX input signal level going to the decoder for
infrared modules that provide rather an inverted output. For exact 3/16 or 1/4 bit wide pulse, the 16X
sampling rate must be used and DLD[3:0] = ’0000’. If DLD[3:0] is not ’0000’, the pulse width can vary.
MCR[5]: Xon-Any Enable (requires EFR bit [4]=1)
• Logic 0 = Disable Xon-Any function (default).
• Logic 1 = Enable Xon-Any function. In this mode any RX character received will enable Xon, resume data
transmission.
MCR[4]: Internal Loopback Enable
• Logic 1 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 12.
MCR[3]: Send Char Immediate (OP2 in Local Loopback Mode)
This bit is used to transmit a character immediately irrespective of the bytes currently in the transmit FIFO. The
data byte must be loaded into the transmit holding register (THR) immediately following the write to this bit (to
set it to a ’1’). In other words, no other register must be accessed between setting this bit and writing to the
THR. The loaded byte will be transmitted ahead of all the bytes in the TX FIFO, immediately after the character
currently being shifted out of the transmit shift register is sent out. The existing line parameters (parity, stop
bits) will be used when composing the character. This bit is self clearing, therefore, must be set before sending
a custom character each time. Please note that the Transmitter must be enabled for this function (MSR[3] = 0).
Also, if software flow control is enabled, the software flow control characters (Xon, Xoff) have higher priority
and will get shifted out before the custom byte is transmitted.
• Logic 0 = Send Char Immediate disabled (default).
• Logic 1 = Send Char Immediate enabled.
In Local Loopback Mode (MCR[4] = 1), this bit acts as the legacy OP2 output and controls the CD bit in the
MSR register as shown in Figure 12. Please make sure that this bit is a ’0’ when exiting the Local Loopback
Mode.
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