XR17V352 Datasheet, PDF (30/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
PRELIMINARY
HIGH PERFORMANCE DUAL PCI EXPRESS UART
REV. P1.0.1
Channel 0 to 1 Transmit Data in 32-bit alignment through the Configuration Register Address
0x0100 and 0x0500
Transmit Data Byte n+3
Transmit Data Byte n+2
Transmit Data Byte n+1
Transmit Data Byte n+0
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
PCI Bus
Data Bit-31
PCI Bus
Data Bit-0
2.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
The THR and RHR register address for channel 0 to channel 1 is shown in Table 10 below. The THR and RHR
for each channel 0 to 1 are located sequentially at address 0x0000 and 0x0200. Transmit data byte is loaded to
the THR when writing to that address and receive data is unloaded from the RHR register when reading that
address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus operation can only
write or read in bytes.
TABLE 10: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH1 (16C550 Compatible)
CH0 0x0000 Read THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH0 0x0000 Write RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x4000 Read THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x4000 Write RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
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