XR17V352 Datasheet, PDF (10/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
PRELIMINARY
HIGH PERFORMANCE DUAL PCI EXPRESS UART
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
0x18h 31:0
RO Unimplemented Base Address Register (returns zeros)
0x1C 31:0
RO Unimplemented Base Address Register (returns zeros)
0x20 31:0
RO Unimplemented Base Address Register (returns zeros)
0x24 31:0
RO Unimplemented Base Address Register (returns zeros)
0x28 31:0
RO Reserved
0x2C 31:16
EWR Subsystem ID (write from external EEPROM by customer)
15:0
EWR Subsystem Vendor ID (write from external EEPROM by cus-
tomer)
0x30 31:0
RO Expansion ROM Base Address (Unimplemented)
0x34 31:8
RO Reserved (returns zeros)
7:0
RO Capability Pointer
0x38 31:0
RO Reserved (returns zeros)
0x3C 31:24
RO Unimplemented MAXLAT
23:16
RO Unimplemented MINGNT
15:8
RO Interrupt Pin, use INTA#.
7:0
RWR Interrupt Line.
0x40 31:0
RO Not implemented or not applicable (return zeros)
0x44 31:0
RO CSR
0x48 31:0
RO Not implemented or not applicable (return zeros)
0x4C 31:0
RO Not implemented or not applicable (return zeros)
0x50 31:16
RO 64-bit address capable
15:8
RO Next Capability Pointer
7:0
RO MSI Capable Capability ID
0x54-0x67 31:0
RO Not implemented or not applicable (return zeros)
0x68 31:16
RO Not implemented or not applicable (return zeros)
15:8
RO Next Capability Pointer
7:0
RO MSI-X Capable Capability ID
0x6C-0x77 31:0
RO Not implemented or not applicable (return zeros)
0x78 31:16
RO PME# support (PME# can be asserted from D3hot and D0)
PCI Power Management 1.2
15:8
RO Next Capability Pointer
7:0
RO Power Management Capability ID
0x7C 31:0
RO No soft reset when transitioning from D3hot to D0 state
REV. P1.0.1
RESET VALUE
(HEX OR BINARY)
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x0000
0x0000
0x00000000
0x000000
0x50
0x00000000
0x00
0x00
0x01
0xXX
0x00000000
0x02106160
0x00000000
0x00000000
0x0080
0x78
0x05
0x00000000
0x0000
0x78
0x11
0x00000000
0x4803
0x80
0x01
0x00000008
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