XR17V352 Datasheet, PDF (60/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
PRELIMINARY
HIGH PERFORMANCE DUAL PCI EXPRESS UART
REV. P1.0.1
4.18 RXTRG[7:0]: Receive FIFO Trigger Level - Write Only
An 8-bit value written to this register, sets the RX FIFO trigger level from 0x00 (zero) to 0xFF (255). The RX
FIFO trigger level generates an interrupt whenever the receive FIFO level rises to this preset trigger level.
4.19 XOFF1, XOFF2, XON1 AND XON2 REGISTERS - Write Only
These registers are used to program the Xoff1, Xoff2, Xon1 and Xon2 control characters respectively.
4.20 XCHAR REGISTER - Read Only
This register gives the status of the last sent control character (Xon or Xoff) and the last received control
character (Xon or Xoff). This register will be reset to 0x00 if, at anytime, the Software Flow Control is disabled.
XCHAR [7:4]: Reserved
XCHAR [3]: Transmit Xon Indicator
If the last transmitted control character was a Xon character or characters (Xon1, Xon2), this bit will be set to a
logic 1. This bit will clear after the read.
XCHAR [2]: Transmit Xoff Indicator
If the last transmitted control character was a Xoff character or characters (Xoff1, Xoff2), this bit will be set to a
logic 1. This bit will clear after the read.
XCHAR [1]: Xon Detect Indicator
If the last received control character was a Xon character, Xon characters (Xon1, Xon2) or an Xon-Any
character, this bit will be set to a logic 1. This bit will clear after the read.
XCHAR [0]: Xoff Detect Indicator
If the last received control character was a Xoff character or characters (Xoff1, Xoff2), this bit will be set to a
logic 1. This bit will clear after the read.
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