XR17V352 Datasheet, PDF (22/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
PRELIMINARY
HIGH PERFORMANCE DUAL PCI EXPRESS UART
REV. P1.0.1
8X sampling rate. Transmit and receive data rates will double by selecting 8X. If using the 4XMODE, the
corresponding bit in this register should be logic 0
8XMODE Register
Individual UART Channel 8X Clock Mode Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 0 0 0 Ch-1 Ch-0
1.4.4 4XMODE [15:8] (default 0x00)
Each bit selects 4X or 16X sampling rate for that UART channel. The 4XMODE register is accessible from the
Device Configuration Registers in all UART channels but the UART channel can only control the bit for that
channel. For example, bit [0] is channel 0 and can only be controlled by channel 0. All other bits are read-only
in channel 0. Logic 0 (default) selects normal 16X sampling (and 8XMODE = 0x00) with logic one selects 4X
sampling rate. Transmit and receive data rates will quadruple by selecting 4X. If using the 8XMODE, the
corresponding bit in this register should be logic 0
4XMODE Register
Individual UART Channel 4X Clock Mode Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 0 0 0 Ch-1 Ch-0
RESET [23:16] (default 0x00)
The 8-bit RESET register provides the software with the ability to reset the UART(s) when there is a need. The
RESET register is accessible from the Device Configuration Registers in all UART channels but the UART
channel can only control the bit for that channel. For example, writing 0xFF to the RESET register in channel 0
will only reset channel 0. Each bit is self-clearing after it is written a logic 1 to perform a reset to that channel.
All registers in that channel will be reset to the default condition, see Table 20 for details. .
RESET Register
Individual UART Channel Reset Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 0 0 0 Ch-1 Ch-0
1.4.5 SLEEP [31:24] (default 0x00)
SLEEP Register
Individual UART Channel Sleep Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 0 0 0 Ch-1 Ch-0
22