XR17V352 Datasheet, PDF (16/64 Pages) Exar Corporation – HIGH PERFORMANCE DUAL PCI EXPRESS UART

XR17V352
PRELIMINARY
HIGH PERFORMANCE DUAL PCI EXPRESS UART
TABLE 5: DEVICE CONFIGURATION REGISTERS SHOWN IN BYTE ALIGNMENT
REV. P1.0.1
ADDRESS [A7:A0]
Ox098
Ox099
0x09A
0x09B
REGISTER
READ/WRITE COMMENT
MPIOINV[15:8] Read/Write MPIO[15:8] input polarity select
MPIOSEL[15:8] Read/Write MPIO[15:8] select
MPIOOD[15:8] Read/Write MPIO[15:8] open-drain output control
Reserved
RESET STATE
Bits [15:8] = 0x00
Bits [15:8] = 0xFF
Bits [15:8] = 0x00
0x00
TABLE 6: DEVICE CONFIGURATION REGISTERS SHOWN IN DWORD ALIGNMENT
ADDRESS
REGISTER
0x0080-0x0083 INTERRUPT (read-only)
0x0084-0x0087
TIMER (read/write)
0x0088-0x008B ANCILLARY1 (read/write)
0x008C-0x008F ANCILLARY2 (read-only)
0x0090-0x0093
MPIO1 (read/write)
0x0094-0x0097
MPIO2 (read/write)
0x0098-0x009B
MPIO3 (read/write)
BYTE 3 [31:24] BYTE 2 [23:16] BYTE 1 [15:8]
BYTE 0 [7:0]
INT3
INT2
INT1
INT0
TIMERMSB
TIMERLSB
Reserved
TIMERCNTL
SLEEP
RESET
4XMODE
8XMODE
MPIOINT[7:0]
REGB
DVID
DREV
MPIOSEL[7:0] MPIOINV[7:0] MPIO3T[7:0] MPIOLVL[7:0]
MPIO3T[7:0] MPIOLVL[15:8] MPIOINT[15:8] MPIOOD[7:0]
Reserved
MPIOOD[15:8] MPIOSEL[15:8] MPIOINV[15:8]
1.4.1 The Global Interrupt Registers - INT0, INT1, INT2 and INT3
The XR17V352 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is an 4-bit indicator representing both channels with each bit
representing each channel from 0 to 1. This permits the interrupt service routine to quickly determine which
UART channels need servicing so that it can go to the appropriate UART channel interrupt service routines.
INT0 bit [0] represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or
modem port status requires service. Other bits in the INT0 register provide indication for the other channels
with bit [1] representing UART channel 1 respectively.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1, INT2 and INT3 registers provide the 24-bit interrupt
status for both channels. bits [10:8] representing channel 0 and bits [13:11] representing channel 1
respectively. All other bits are reserved. Both channel interrupts status are available with a single DWORD read
operation. This feature allows the host another method to quickly service the interrupts, thus reducing the
service interval and host bandwidth requirement.
Note that the interrupts reported in this register is specific to each UART channel. If there is a global interrupt
such as the wake-up interrupt, timer/counter interrupt or MPIO interrupt, they would be reported in the 3-bit
code for channel 0 in INT1.
GLOBAL INTERRUPT REGISTER (DWORD) [default 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:8]
INT0 [7:0]
All bits start up zero. A special interrupt condition is generated by the V352 upon awakening from sleep after
both channels were put to sleep mode earlier. This wake-up interrupt is cleared by a read to the INT0 register.
Figure 4 shows the 4-byte interrupt register and its make up.
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