XR17C152 Datasheet, PDF (8/62 Pages) Exar Corporation – 5V PCI BUS DUAL UART

XR17C152
5V PCI BUS DUAL UART
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REV. 1.2.0
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
The PCI local bus configuration space registers are responsible for setting up the device’s operating
environment in the PCI local bus. The pre-defined operating parameters of the device are read by the PCI bus
plug-and-play auto-configuration manager in the operating system. After the PCI bus has collected all data
from every device/card on the bus, it defines and downloads the memory mapping information to each device/
card about their individual operation memory address location and conditions. The operating memory mapped
address location is downloaded into the Base Address Register (BAR) register, 0x10. The plug-and-play auto
configuration feature is only available when an external 93C46 EEPROM is used. The EEPROM contains the
device vendor and sub-vendor data required by the auto-configuration setup.
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX)
0x00 31:16
RWR^{1 Device ID (Exar device ID number or from EEPROM)}
0x0152
15:0
RWR^{1 Vendor ID (Exar ID or from EEPROM) assigned by PCISIG}
0x13A8
0x04
31
30
29:28
RWC
RWC
RO
Parity error detected. Cleared by writing a logic 1.
System error detected. Cleared by writing a logic 1.
Unused
0000
27
R-Reset Target Abort. Set whenever 152 terminates with a target abort.
0
26:25
RO DEVSEL# timing.
00
24
RO Unimplemented bus master error reporting bit
0
23
RO Fast back to back transactions are supported
1
22:16
RO Reserved Status bits
000 0000
15:9,7,
5,4,3,2
RO Command bits (reserved)
0x0000
8
RWR SERR# driver enable. Logic 1=enable driver and 0=disable
0
driver
6
RWR Parity error enable. Logic 1=respond to parity error and 0=ignore
0
1
RWR Command controls a device’s response to mem space accesses:
0
0=disable mem space accesses, 1=enable mem space accesses
0
RO Command controls a device’s response to I/O space accesses:
0
0 = disable I/O space accesses 1 = enable I/O space accesses
0x08 31:8
RO Class Code (Simple 550 Communication Controller).
0x070002
7:0
RO Revision ID (Exar device revision number)
Current Rev. value
0x0C 31:24
RO BIST (Built-in Self Test)
0x00
23:16
RO Header Type (a single function device with one BAR)
0x00
15:8
RO Unimplemented Latency Timer (needed only for bus master)
0x00
7:0
RO Unimplemented Cache Line Size
0x00
0x10 31:10
RWR Memory Base Address Register (BAR)
0x00 00 00
9:0
RO Claims a 1K address space for the memory mapped UARTs
00 0000 0000
0x14 31:0
RO Unimplemented Base Address Register (returns zeros)
0x00000000
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