XR17C152 Datasheet, PDF (61/62 Pages) Exar Corporation – 5V PCI BUS DUAL UART

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XR17C152
5V PCI BUS DUAL UART
REV. 1.2.0
FIGURE 10. TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................................... 26
FIGURE 11. TRANSMIITTER OPERATION IN FIFO AND FLOW CONTROL MODE .......................................................................................... 26
4.3 RECEIVER ......................................................................................................................................... 27
4.3.1 Receive Holding Register (RHR) - Read-Only ......................................................................................... 27
4.3.2 Receiver Operation in non-FIFO Mode ................................................................................................... 27
FIGURE 12. RECEIVER OPERATION IN NON-FIFO MODE ......................................................................................................................... 27
4.3.3 Receiver Operation with FIFO.................................................................................................................. 28
4.4 AUTOMATIC HARDWARE (RTS/CTS OR DTR/DSR) FLOW CONTROL OPERATION ............................... 28
FIGURE 13. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE ................................................................................................ 28
TABLE 10: AUTO RTS/CTS OR DTR/DSR FLOW CONTROL SELECTION ................................................................................................. 28
FIGURE 14. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION ............................................................................................. 29
4.5 INFRARED MODE ............................................................................................................................... 30
FIGURE 15. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING ................................................................................. 30
4.6 INTERNAL LOOPBACK ........................................................................................................................ 31
4.7 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ....................... 31
FIGURE 16. INTERNAL LOOP BACK FUNCTION IN EACH UART CHANNEL.................................................................................................. 31
TABLE 11: UART CHANNEL CONFIGURATION REGISTERS........................................................................................................... 32
TABLE 12: UART CHANNEL CONFIGURATION REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED BY EFR BIT-4................ 33
4.8 REGISTERS ....................................................................................................................................... 34
4.8.1 Receive Holding Register (RHR) - Read-Only ......................................................................................... 34
4.8.2 Transmit Holding Register (THR) - Write-Only......................................................................................... 34
4.8.3 Baud Rate Generator Divisors (DLL and DLM) - Read/Write................................................................... 34
4.8.4 Interrupt Enable Register (IER) - Read/Write........................................................................................... 34
IER versus Receive FIFO Interrupt Mode Operation ......................................................................................... 34
IER versus Receive/Transmit FIFO Polled Mode Operation.............................................................................. 34
4.8.5 Interrupt Status Register (ISR) - Read-Only............................................................................................. 35
TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL............................................................................................................................. 36
4.8.6 FIFO Control Register (FCR) - Write-Only ............................................................................................... 37
TABLE 14: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ................................................................................................... 38
4.8.7 Line Control Register (LCR) - Read/Write................................................................................................ 39
4.8.8 Modem Control Register (MCR) - Read/Write.......................................................................................... 40
TABLE 15: PARITY SELECTION................................................................................................................................................................ 40
4.8.9 Line Status Register (LSR) - Read/Only .................................................................................................. 41
4.8.10 Modem Status Register (MSR) - Read-Only .......................................................................................... 42
4.8.11 Modem Status Register (MSR) - Write-Only .......................................................................................... 43
TABLE 16: AUTO RS485 HALF-DUPLEX DIRECTION CONTROL DELAY FROM TRANSMIT-TO-RECEIVE......................................................... 43
4.8.12 SCRATCH PAD REGISTER (SPR) - Read/Write .................................................................................. 44
4.8.13 FEATURE CONTROL REGISTER (FCTR) - Read/Write ..................................................................... 44
4.8.14 Enhanced Feature Register (EFR) - Read/Write.................................................................................... 45
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED ........................................................................ 45
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS ............................................................................................................................... 46
4.8.15 TXCNT[7:0]: Transmit FIFO Level Counter - Read-Only ....................................................................... 47
4.8.16 TXTRG [7:0]: Transmit FIFO Trigger Level - Write-Only........................................................................ 47
4.8.17 RXCNT[7:0]: Receive FIFO Level Counter - Read-Only ........................................................................ 47
4.8.18 RXTRG[7:0]: Receive FIFO Trigger Level - Write-Only ......................................................................... 47
TABLE 19: UART RESET CONDITIONS ............................................................................................................................................. 48
5.0 programming Examples ....................................................................................................... 49
5.1 UNLOADING RECEIVE DATA USING THE SPECIAL RECEIVE FIFO DATA WITH STATUS ......................... 49
ABSOLUTE MAXIMUM RATINGS .................................................................................. 50
ELECTRICAL CHARACTERISTICS................................................................................ 50
DC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING .............................................................. 50
AC ELECTRICAL CHARACTERISTICS FOR 5V SIGNALING ................................................................ 51
FIGURE 17. PCI BUS CONFIGURATION SPACE REGISTERS READ AND WRITE OPERATION ........................................................................ 52
FIGURE 18. DEVICE CONFIGURATION AND UART REGISTERS READ OPERATION FOR A BYTE OR DWORD.............................................. 53
FIGURE 19. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND TRANSMIT DATA BURST WRITE OPERATION ............................ 54
FIGURE 20. DEVICE CONFIGURATION REGISTERS, UART REGISTERS AND RECEIVE DATA BURST READ OPERATION ............................... 55
FIGURE 21. 5V PCI BUS CLOCK............................................................................................................................................................ 56
FIGURE 22. TRANSMIT DATA INTERRUPT AT TRIGGER LEVEL .................................................................................................................. 57
FIGURE 23. RECEIVE DATA READY INTERRUPT AT TRIGGER LEVEL ......................................................................................................... 57
PACKAGE DIMENSIONS ................................................................................................ 58
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