XR17C152 Datasheet, PDF (26/62 Pages) Exar Corporation – 5V PCI BUS DUAL UART

XR17C152
5V PCI BUS DUAL UART
FIGURE 10. TRANSMITTER OPERATION IN NON-FIFO MODE
áç
REV. 1.2.0
D a ta
B y te
16X or 8X
C lock
(8XM ODE
R egister)
Transm it
H olding
R egister
(T H R )
TH R Interrupt (ISR bit-1)
Enabled by IER bit-1
Transm it Shift R egister (TSR)
M
L
S
S
B
B
T X N O F IF O 1
4.2.3 Transmitter Operation in FIFO mode
The host may fill the transmit FIFO with up to 64 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level (see TXTRG register). The transmit empty
interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
Furthermore, with the RS485 half-duplex direction control enabled (FCTR bit-5=1) the source of the transmit
empty interrupt changes to TSR empty instead of THR empty. This is to ensure the RTS# output is not
changed until the last stop bit of the last character is shifted out.
4.2.4 Auto RS485 Operation
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled during
powerup or reset by the EN485# pin or in software by FCTR bit-5. While transmitting, the RTS# or DTR# signal
is HIGH. The RTS# or DTR# signal changes from a HIGH to a LOW after a specified delay indicated in
MSR[7:4] following the last stop bit of the last character that has been transmitted. This helps in turning around
the transceiver to receive the remote station’s response. The delay optimizes the time needed for the last
transmission to reach the farthest station on a long cable network before switching off the line driver. This delay
prevents undesirable line signal disturbance that causes signal degradation. It also changes the transmitter
empty interrupt to TSR empty instead of THR empty.
FIGURE 11. TRANSMIITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transm it
Data Byte
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
Auto Softw are Flow C ontrol
Transm it
F IF O
(64-Byte)
TH R Interrupt (ISR bit-1) falls
below Program m ed Trigger
Level (TXTRG) and then
when becomes em pty. FIFO
is Enabled by FCR bit-0=1
16X or 8X Clock
(8XM O DE Register)
Transm it Data Shift R egister
(TSR)
Auto CTS Flow C ontrol (CTS# pin)
TXFIFO 1
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