XR17C152 Datasheet, PDF (36/62 Pages) Exar Corporation – 5V PCI BUS DUAL UART

XR17C152
5V PCI BUS DUAL UART
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REV. 1.2.0
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by RX trigger level.
• RXRDY Time-out is by the a 4-char plus 12 bits delay timer if the RX FIFO level is less than the RX trigger
level.
• TXRDY is by LSR bit-5 (or bit-6 in auto RS485 control).
• MSR is by any of the MSR bits, 0, 1, 2 and 3.
• Receive Xon/Xoff/Special character is by detection of a Xon, Xoff or Special character.
• CTS#/DSR# is by a change of state on the input pin (from LOW to HIGH) with auto flow control enabled,
EFR bit-7, and depending on selection of MCR bit-2.
• RTS#/DTR# is when its receiver changes the state of the output pin (from LOW to HIGH) during auto RTS/
DTR flow control enabled by EFR bit-6 and selection of MCR bit-2.
• Wake-up Indicator: when the UART comes out of sleep mode.
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY is cleared by reading data until FIFO falls below the trigger level.
• RXRDY Time-out is cleared by reading data until the RX FIFO is empty.
• TXRDY interrupt is cleared by a read to the ISR register.
• MSR interrupt is cleared by a read to the MSR register.
• Xon or Xoff character interrupt is cleared by a read to ISR register.
• Special character interrupt is cleared by a read to ISR register or after the next character is received.
• RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
• Wake-up Indicator is cleared by a read to the INT0 register.
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TABLE 13: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF THE INTERRUPT
LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1
BIT-0
1
0
0
0
1
1
0 _{LSR (Receiver Line Status Register)}
2
0
0
0
1
0
0 _{RXRDY (Received Data Ready)}
3
0
0
1
1
0
0 _{RXRDY (Receive Data Time-out)}
4
0
0
0
0
1
0 _{TXRDY (Transmitter Holding Register Empty)}
5
0
0
0
0
0
0 _{MSR (Modem Status Register)}
6
0
1
0
0
0
0 _{RXRDY (Received Xon/Xoff or Special character)}
7
1
0
0
0
0
0 _{CTS#/DSR#, RTS#/DTR# change of state}
X
0
0
0
0
0
1 _{None (default)}
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels 1, 2, 3 and 4 (See Interrupt
Source Table 13).
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