XR17C152 Datasheet, PDF (24/62 Pages) Exar Corporation – 5V PCI BUS DUAL UART

XR17C152
5V PCI BUS DUAL UART
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REV. 1.2.0
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR
AND RHR IN 8-BIT FORMAT
The THR and RHR register address for channel 0 to channel 1 is shown in Table 8 below. The THR and RHR
for each channel 0 tand 1 are located sequentially at address 0x0000 and 0x0200. Transmit data byte is
loaded to the THR when writing to that address and receive data is unloaded from the RHR register when
reading that address. Both THR and RHR registers are 16C550 compatible in 8-bit format, so each bus
operation can only write or read in bytes.
TABLE 8: TRANSMIT AND RECEIVE DATA REGISTER IN BYTE FORMAT, 16C550 COMPATIBLE
THR and RHR Address Locations For CH0 to CH1 (16C550 Compatible)
CH0 0x000 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH0 0x000 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x200 Write THR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
CH1 0x200 Read RHR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
4.0 UART
There are 2 UARTs [channels 1:0] in the 152. Each has its own 64-byte of transmit and receive FIFO, a set of
16550 compatible control and status registers, and a baud rate generator for individual channel data rate
setting. Eight additional registers per UART were added for the EXAR enhanced features.
4.1 Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler to divide
the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG further
divides this clock by a programmable divisor between 1 and (2¹⁶ -1) to obtain a 16X or 8X sampling clock of
the serial data rate. The sampling clock is used by the transmitter for data bit shifting and receiver for data
sampling. The BRG divisor (DLL and DLM registers) defaults to a random value upon power up. Therefore, the
BRG must be programmed during initialization to the operating data rate.
FIGURE 9. BAUD RATE GENERATOR
To Channel 1
XTAL1
XTAL2
Crystal
Osc/
Buffer
Prescaler
Divide by 1
Prescaler
Divide by 4
DLL and DLM
Registers
MCR Bit-7=0
(default)
Baud Rate
Generator
Logic
MCR Bit-7=1
16X or 8X
Sampling
Rate Clock to
Transmitter
and Receiver
Programming the Baud Rate Generator Registers DLM and DLL provides the capability for selecting the
operating data rate. Table 9 shows the standard data rates available with a 14.7456 MHz crystal or external
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