XR16C2850 Datasheet, PDF (8/43 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
2.5 CHANNEL A AND B INTERNAL REGISTERS
Each UART channel in the 2850 has a set of en-
hanced registers for control, monitoring and data
loading and unloading. The configuration register set
is compatible to those already available in the stan-
dard single 16C550 and dual ST16C2550. These
registers function as data holding registers (THR/
RHR), interrupt status and control registers (ISR/
IER), a FIFO control register (FCR), receive line sta-
tus and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable da-
ta rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabili-
ties, the 2850 offers enhanced feature registers (EM-
SR, FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG,
FC) that provide automatic RTS and CTS hardware
flow control, Xon/Xoff software flow control, automatic
RS-485 half-duplex direction output enable/disable,
FIFO trigger level control, and FIFO level counters.
All the register functions are discussed in full detail
later in “UART INTERNAL REGISTERS” on page 18.
2.6 DMA MODE
The device does not support direct memory access.
The DMA Mode (a legacy term) in this document
doesn’t mean “direct memory access” but refers to
data block transfer operation. The DMA mode affects
the state of the RXRDY# A/B and TXRDY# A/B output
pins. The transmit and receive FIFO trigger levels
provide additional flexibility to the user for block mode
operation. The LSR bits 5-6 provide an indication
when the transmitter is empty or has an empty loca-
tion(s) for more data. The user can optionally operate
the transmit and receive FIFO in the DMA mode
(FCR bit-3=1). When the transmit and receive FIFO
are enabled and the DMA mode is disabled (FCR bit-
3 = 0), the 2850 is placed in single-character mode
for data transmit or receive operation. When DMA
mode is enabled (FCR bit-3 = 1), the user takes ad-
vantage of block mode operation by loading or un-
loading the FIFO in a block sequence determined by
the programmed trigger level. In this mode, the 2850
sets the TXRDY# pin when the transmit FIFO be-
comes full, and sets the RXRDY# pin when the re-
ceive FIFO becomes empty. The following table
shows their behavior. Also see Figures 18
through 23.
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
FCR BIT-0=0
(FIFO DISABLED)
RXRDY# A/B 0 = 1 byte.
1 = no data.
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = at least 1 byte in FIFO
1 = FIFO empty.
FCR Bit-3 = 1
(DMA Mode Enabled)
1 to 0 transition when FIFO reaches the trigger
level, or timeout occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B 0 = THR empty.
1 = byte in THR.
0 = FIFO empty.
1 = at least 1 byte in FIFO.
0 = FIFO has at least 1 empty location.
1 = FIFO is full.
2.7 INTA AND INTB OUPUTS
The INTA and INTB interrupt output output changes
according to the operating mode and enahnced fea-
tures setup. Table 3 and 4 summarize the operating
behavior for the transmitter and receiver. Also see
Figures 18 through 23.
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER
Auto RS485 Mode
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin
NO
0 = a byte in THR
1 = THR empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO empty
INTA/B Pin
YES
0 = a byte in THR
1 = transmitter empty
0 = FIFO above trigger level
1 = FIFO below trigger level or transmitter empty
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