XR16C2850 Datasheet, PDF (4/43 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
NAME
RXA
RXB
40-PDIP
PIN #
10
9
44-PLCC
PIN #
11
10
RTSA#
32
36
RTSB#
24
27
CTSA#
36
40
CTSB#
25
28
DTRA#
33
37
DTRB#
34
38
DSRA#
37
41
DSRB#
22
25
CDA#
38
42
CDB#
19
21
RIA#
39
43
RIB#
23
26
OP2A#
31
35
OP2B#
13
15
ANCILLARY SIGNALS
XTAL1
16
18
XTAL2
17
19
HDCNTL#
-
-
48-TQFP
PIN #
5
4
33
22
38
23
34
35
39
20
40
16
41
21
32
9
13
14
37
TYPE
DESCRIPTION
I UART channel A Receive Data or infrared receive data.
Normal receive data input must idle at logic 1 condition.
The infrared receiver pulses typically idles at logic 0 but
can be inverted by software control prior going in to the
decoder, see MCR[6] and FCTR[2]. If this pin is not used,
tie it to VCC or pull it high via a 100k ohm resistor.
O UART channel A or B Request-to-Send (active low) or
general purpose output. This output must be asserted
prior to using auto RTS flow control, see EFR[6], MCR[1],
FCTR[1:0], EMSR[5:4] and IER[6].
I UART channel A or B Clear-to-Send (active low) or gen-
eral purpose input. It can be used for auto CTS flow con-
trol, see EFR[7], and IER[7]. This input should be
connected to VCC when not used.
O UART channel A or B Data-Terminal-Ready (active low)
or general purpose output. If it is not used, leave it uncon-
nected.
I UART channel A or B Data-Set-Ready (active low) or
general purpose input. This input should be connected to
VCC when not used. This input has no effect on the
UART.
I UART channel A or B Carrier-Detect (active low) or gen-
eral purpose input. This input should be connected to
VCC when not used. This input has no effect on the
UART.
I UART channel A or B Ring-Indicator (active low) or gen-
eral purpose input. This input should be connected to
VCC when not used. This input has no effect on the
UART.
O Output Port 2 channel A or B - The output state is defined
by the user and through the software setting of MCR[3].
INTA or INTB is set to the active mode and OP2A# or
OP2B# output to a logic 0 when MCR[3] is set to a logic
1. INTA or INTB is set to the three state mode and OP2A#
or OP2B# to a logic 1 when MCR[3] is set to a logic 0.
See MCR[3]. This output should not be used as a general
output else it will disturb the INTA or INTB output function-
ality.
I Crystal or external clock input.
O Crystal or buffered clock output.
I RS-485 half duplex directional control for channel A and B
(active low). Connect to VCC for normal RTS# function
and connect to GND for RS-485 half duplex direction con-
trol. RTS# pin goes low for transmit and high for receive.
This pin is wire “OR-ed” with FCTR[3]. See FCTR[3].
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