XR16C2850 Datasheet, PDF (14/43 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART
UARTA
Receiver FIFO
RXA
Trigger Reached
Remote UART
UARTB
TXB
Transmitter
Auto RTS
Trigger Level
Transmitter
RTSA#
TXA
CTSB#
RXB
Auto CTS
Monitor
Receiver FIFO
Trigger Reached
Auto CTS
Monitor
CTSA#
RTSB#
Auto RTS
Trigger Level
RTSA#
CTSB#
TXB
Assert RTS# to Begin
Transmission
1
ON
2
ON
3
Data Starts
4
RXA FIFO
Receive
INTA
(RXA FIFO
Data
RX FIFO
Trigger Level
5
Interrupt)
OFF
7
8 ^OFF
10 ON
11
ON
6 _Suspend
Restart
9
RTS High
Threshold
RTS Low
Threshold
RX FIFO
12 _{Trigger Level}
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its transmit
shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9), UARTA
re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until next
receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB with
RTSB# and CTSA# controlling the data flow.
2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
When software flow control is enabled (See
Table 15), the 2850 compares one or two sequential
receive data characters with the programmed Xon or
Xoff-1,2 character value(s). If receive character(s)
(RX) match the programmed values, the 2850 will halt
transmission (TX) as soon as the current character
has completed transmission. When a match occurs,
the Xoff (if enabled via IER bit-5) flag will be set and
the interrupt output pin will be activated. Following a
suspension due to a match of the Xoff character, the
2850 will monitor the receive data stream for a match
to the Xon-1,2 character. If a match is found, the 2850
will resume operation and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit
flow control registers to a logic 0. Following reset the
user can write any Xon/Xoff value desired for soft-
ware flow control. Different conditions can be set to
detect Xon/Xoff characters (See Table 15) and sus-
pend/resume transmissions. When double 8-bit Xon/
Xoff characters are selected, the 2850 compares two
consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and
controls TX transmissions accordingly. Under the
above described flow control mechanisms, flow con-
trol characters are not placed (stacked) in the user
accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and
flow control needs to be executed, the 2850 automat-
ically sends an Xoff message (when enabled) via the
serial TX output to the remote modem. The 2850
sends the Xoff-1,2 characters two-character-times (=
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