XR16C2850 Datasheet, PDF (24/43 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE
The Line Control Register is used to specify the asyn-
chronous data communication format. The word or
character length, the number of stop bits, and the par-
ity are selected by writing the appropriate bits in this
register.
LCR[1-0]: TX and RX Word Length Select
These two bits specify the word length to be transmit-
ted or received.
BIT-1
BIT-0
WORD LENGTH
ter. The receiver must be programmed to check the
same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the
forced parity format.
• LCR BIT-5 = logic 0, parity is not forced (default).
• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity
bit is forced to a logical 1 for the transmit and
receive data.
TABLE 11: PARITY SELECTION
0
0
0
1
1
0
5 (default)
6
7
LCR BIT-5 LCR BIT-4 LCR BIT-3
X
X
0
0
0
1
PARITY SELECTION
No parity
Odd parity
1
1
8
0
1
1
Even parity
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in con-
junction with the programmed word length.
BIT-2
WORD
LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The
parity bit is a simple way used in communications for
data integrity check. See Table 11 for parity selection
summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the trans-
mission while the receiver checks for parity error of
the data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic
1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an
odd number of logic 1’s in the transmitted character.
The receiver must be programmed to check the
same format (default).
• Logic 1 = EVEN Parity is generated by forcing an
even number of logic 1’s in the transmitted charac-
1
0
1
1
1
Force parity to mark,
“1”
1
Forced parity to
space, “0”
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to
a “space’, logic 0, state). This condition remains, until
disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition. (default)
• Logic 1 = Forces the transmitter output (TX) to a
“space”, logic 0, for alerting the remote receiver of a
line break condition.
LCR[7]: Baud Rate Divisors Enable
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.7 MODEM CONTROL REGISTER (MCR) OR GEN-
ERAL PURPOSE OUTPUTS CONTROL - READ/
WRITE
The MCR register is used for controlling the serial/
modem interface signals or general purpose inputs/
outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the mo-
dem interface is not used, this output may be used as
a general purpose output.
• Logic 0 = Force DTR# output to a logic 1 (default).
• Logic 1 = Force DTR# output to a logic 0.
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