XR16C2850 Datasheet, PDF (3/43 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

XR16C2850
REV. 2.0.0
PIN DESCRIPTIONS
3.3V AND 5V DUART WITH 128-BYTE FIFO
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NAME
40-PDIP
PIN #
44-PLCC
PIN #
DATA BUS INTERFACE
A2
26
29
A1
27
30
A0
28
31
D7
8
9
D6
7
8
D5
6
7
D4
5
6
D3
4
5
D2
3
4
D1
2
3
D0
1
2
IOR#
21
24
48-TQFP
PIN #
26
27
28
3
2
1
48
47
46
45
44
19
IOW#
18
20
15
CSA#
14
16
10
CSB#
15
17
11
INTA
30
33
30
INTB
29
32
29
TXRDYA#
-
TXRDYB#
-
1
43
12
6
RXRDYA#
-
RXRDYB#
-
34
31
23
18
MODEM OR SERIAL I/O INTERFACE
TXA
11
13
7
TXB
12
14
8
TYPE
DESCRIPTION
I Address data lines [2:0]. These 3 address lines select
one of the internal registers in UART channel A/B during
a data bus transaction.
I/O Data bus lines [7:0] (bidirectional).
I Input/Output Read Strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data
byte from an internal register pointed to by the address
lines A2:A0. The data byte is placed on the data bus to
allow the host processor to read it on the rising edge.
IOR# must never be active together with IOW#.
I Input/Output Write Strobe (active low). The falling edge
instigates an internal write cycle and the rising edge
transfers the data byte on the data bus to an internal reg-
ister pointed by the address lines. IOW# must never be
active together with IOR#.
I UART channel select (active low) to enable UART chan-
nel A or B in the device for data bus operation.
O UART channel A or B Interrupt output. The output state is
defined by the user through the software setting of
MCR[3]. INTA or INTB is set to the active mode and
OP2A# or OP2B# output to a logic 0 when MCR[3] is set
to a logic 1. INTA or INTB is set to the three state mode
and OP2A# or OP2B# to a logic 1 when MCR[3] is set to
a logic 0 (default). See MCR[3].
O UART channel A or B Transmitter Ready (active low).
The output provides the TX FIFO/THR status for transmit
channel A or B. See Table 2 on page 8. If it is not used,
leave it unconnected.
O UART channel A or B Receiver Ready (active low). This
output provides the RX FIFO/RHR status for receive
channel A or B. See Table 2 on page 8. If it is not used,
leave it unconnected.
O UART channel A or B Transmit Data or infrared encoder
data. Standard transmit and receive interface is enabled
when MCR[6] = 0. In this mode, the TX signal will be a
logic 1 during reset or idle (no data). Infrared IrDA trans-
mit and receive interface is enabled when MCR[6] = 1. In
the Infrared mode, the inactive state (no data) for the
Infrared encoder/decoder interface is a logic 0. If it is not
used, leave it unconnected.
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