XR16C2850 Datasheet, PDF (16/43 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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3.3V AND 5V DUART WITH 128-BYTE FIFO
XR16C2850
REV. 2.0.0
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
C h a ra cte r
Data Bits
TX Data 0 ¹ 0 ¹ 0 0 ^{1 1} 0 ¹
Transm it
IR Pulse
(TX Pin)
Receive
IR Pulse
(RX pin)
RX Data
Bit Tim e
3/16 Bit Tim e
1/2 Bit Tim e
IrEncoder-1
Bit Time
1/16 Clock Delay
0 1 0 1 0 0 11 0 1
Data Bits
Character
IRdecoder-1
2.19 SLEEP MODE WITH AUTO WAKE-UP
The 2850 supports low voltage system designs,
hence, a sleep mode is included to reduce its power
consumption when the chip is not actively used. With
EFR bit-4 and IER bit-4 of both channels enabled (set
to a logic 1), the 2850 DUART enters sleep mode
when no interrupt is pending for both channels. The
2850 stops its crystal oscillator to further conserve
power in the sleep mode. User can check the XTAL2
pin for no clock output as an indication that the device
has entered the sleep mode. The 2850 resumes nor-
mal operation by any of the following: a receive data
start bit transition (logic 1 to 0), a change of logic
state on any of the modem or general purpose input
pins: CTS#, DSR#, CD#, RI# or a transmit data byte
is loaded to the THR/FIFO by the user. If the 2850 is
awakened by one of the above conditions, it will re-
turn to the sleep mode automatically after all inter-
rupting condition have been serviced and cleared. In
any case, the sleep mode will not be entered while an
interrupt is pending from channel A or B. The 2850
will stay in the sleep mode of operation until it is dis-
abled by setting IER bit-4 to a logic 0.
A word of caution: owing to the starting up delay of
the crystal oscillator after waking up from sleep
mode, the first few receive characters may be lost. Al-
so, make sure the RX A/B inputs are idling at logic 1
or “marking” condition during sleep mode to avoid re-
ceiving a “break” condition upon the restart. This may
occur when the external interface transceivers (RS-
232, RS-485 or another type) are also put to sleep
mode and cannot maintain the “marking” condition.
To avoid this, the system design engineer can use a
47k ohm pull-up resistor on the RXA and RXB pins.
2.20 INTERNAL LOOPBACK
The 2850 UART provides an internal loopback capa-
bility for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register
bit-4 to logic 1. All regular UART functions operate
normally. Figure 13 shows how the modem port sig-
nals are re-configured. Transmit data from the trans-
mit shift register output is internally routed to the re-
ceive shift register input allowing the system to re-
ceive the same data that it was sending. The TX pin
is held at logic 1 or mark condition while RTS# and
DTR# are de-asserted, and CTS#, DSR# CD# and
RI# inputs are ignored. Caution: the RX input must be
held to a logic 1 during loopback test else upon exit-
ing the loopback test the UART may detect and report
a false “break” signal.
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