XR16C2850 Datasheet, PDF (42/43 Pages) Exar Corporation – 3.3V AND 5V DUART WITH 128-BYTE FIFO

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XR16C2850
3.3V AND 5V DUART WITH 128-BYTE FIFO
REV. 2.0.0
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS............................................................................................................................................. 1
FEATURES .................................................................................................................................................. 1
FIGURE 1. XR16C2850 BLOCK DIAGRAM ................................................................................................................................................ 1
FIGURE 2. PIN OUT ASSIGNMENT............................................................................................................................................................. 2
ORDERING INFORMATION ............................................................................................................................. 2
PIN DESCRIPTIONS .......................................................................................................... 3
DATA BUS INTERFACE........................................................................................................................... 3
MODEM OR SERIAL I/O INTERFACE ..................................................................................................... 3
ANCILLARY SIGNALS.............................................................................................................................. 4
1.0 Product DESCRIPTION ........................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................... 7
2.1 CPU INTERFACE ................................................................................................................................. 7
FIGURE 3. XR16C2850 DATA BUS INTERCONNECTIONS......................................................................................................................... 7
2.2 DEVICE RESET .................................................................................................................................... 7
2.3 DEVICE IDENTIFICATION AND REVISION ................................................................................................ 7
2.4 CHANNEL A AND B SELECTION ............................................................................................................ 7
TABLE 1: CHANNEL A AND B SELECT ....................................................................................................................................................... 7
2.5 CHANNEL A AND B INTERNAL REGISTERS ............................................................................................ 8
2.6 DMA MODE ........................................................................................................................................ 8
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE .................................................................................................... 8
2.7 INTA AND INTB OUPUTS .................................................................................................................... 8
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER................................................................................................................ 8
2.8 CRYSTAL OSCILLATOR OR EXT. CLOCK INPUT ...................................................................................... 9
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER....................................................................................................................... 9
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS ........................................................................................................................................ 9
2.9 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 9
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE ................................................................................................... 9
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER ............................................................................................................................ 10
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK.............................................................................. 10
2.10 TRANSMITTER ................................................................................................................................. 11
2.10.1 Transmit Holding Register (THR) - Write Only ....................................................................................... 11
2.10.2 Transmitter Operation in non-FIFO Mode .............................................................................................. 11
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE...................................................................................................................... 11
2.10.3 Transmitter Operation in FIFO Mode ..................................................................................................... 11
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE............................................................................................. 11
2.11 RECEIVER ....................................................................................................................................... 12
2.11.1 Receive Holding Register (RHR) - Read-Only ....................................................................................... 12
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE ........................................................................................................................... 12
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE............................................................................... 13
2.12 AUTO RTS (HARDWARE) FLOW CONTROL ....................................................................................... 13
2.13 AUTO RTS HYSTERESIS ................................................................................................................. 13
2.14 AUTO CTS FLOW CONTROL ........................................................................................................... 13
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION .............................................................................................................. 14
2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................... 14
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL....................................................................................................................... 15
2.16 SPECIAL CHARACTER DETECT ........................................................................................................ 15
2.17 AUTO RS485 HALF-DUPLEX CONTROL ........................................................................................... 15
2.18 INFRARED MODE ............................................................................................................................. 15
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING ................................................................................. 16
2.19 SLEEP MODE WITH AUTO WAKE-UP ............................................................................................... 16
2.20 INTERNAL LOOPBACK ..................................................................................................................... 16
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B........................................................................................................................ 17
3.0 UART INTERNAL REGISTERS ............................................................................................. 18
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ............................................................................................. 18
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