XR16L2750_05 Datasheet, PDF(7/48 Page) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

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XR16L2750_05 Datasheet, PDF (7/48 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

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REV. 1.2.1

XR16L2750

2.25V TO 5.5V DUART WITH 64-BYTE FIFO

2.0 FUNCTIONAL DESCRIPTIONS

2.1 CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The 2750 data interface supports the Intel compatible types of CPUs and it is compatible to

the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus

transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share

the same data bus for host operations. The data bus interconnections are shown in Figure 3.

FIGURE 3. XR16L2750 DATA BUS INTERCONNECTIONS

IOR#

IOW#

UART_CSA#

UART_CSB#

UART_INTA

UART_INTB

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

UART_RESET

IOR#

IOW#

UART

Channel A

CSA#

CSB#

INTA

INTB

UART

Channel B

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

VCC

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

RIA#

OP2A#

TXB

RXB

DTRB#

RTSB#

CTSB#

DSRB#

CDB#

RIB#

OP2B#

RESET

GND

VCC

Serial Interface of

RS-232, RS-485

Serial Interface of

RS-232, RS-485

2750int

2.2 5-Volt Tolerant Inputs

The 2750 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the 2750 is

operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial

transceiver that is operating at 5V. Caution: XTAL1 is not 5 volt tolerant.

2.3 Device Reset

The RESET input resets the internal registers and the serial interface outputs in both channels to their default

state (see Table 16). An active high pulse of longer than 40 ns duration will be required to activate the reset

function in the device.

2.4 Device Identification and Revision

The XR16L2750 provides a Device Identification code and a Device Revision code to distinguish the part from

other devices and revisions. To read the identification code from the part, it is required to set the baud rate

generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x0A for the

XR16L2750 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01

means revision A.

2.5 Channel A and B Selection

The UART provides the user with the capability to bi-directionally transfer information between an external

CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the

user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the

UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,

but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in

Table 1.

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