XR16L2750_05 Datasheet, PDF (47/48 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

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REV. 1.2.1
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS ............................................................................................................................................... 1
FEATURES ..................................................................................................................................................... 1
FIGURE 1. XR16L2750 BLOCK DIAGRAM ......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION ................................................................................................................................ 2
PIN DESCRIPTIONS ......................................................................................................... 3
1.0 PRODUCT DESCRIPTION .................................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 7
2.1 CPU INTERFACE ............................................................................................................................................. 7
FIGURE 3. XR16L2750 DATA BUS INTERCONNECTIONS.................................................................................................................... 7
2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 7
2.3 DEVICE RESET ................................................................................................................................................ 7
2.4 DEVICE IDENTIFICATION AND REVISION .................................................................................................... 7
2.5 CHANNEL A AND B SELECTION ................................................................................................................... 7
TABLE 1: CHANNEL A AND B SELECT ............................................................................................................................................... 8
2.6 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 8
2.7 DMA MODE ...................................................................................................................................................... 8
TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE............................................................................................. 8
2.8 INTA AND INTB OUTPUTS .............................................................................................................................. 9
TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER ........................................................................................................ 9
TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................... 9
2.9 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ............................................................................. 9
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 9
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE .......................................................................................... 10
2.10 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 10
FIGURE 6. BAUD RATE GENERATOR AND PRESCALER ..................................................................................................................... 10
TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 11
2.11 TRANSMITTER ............................................................................................................................................. 11
2.11.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 11
2.11.2 TRANSMITTER OPERATION IN NON-FIFO MODE ................................................................................................ 11
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 12
2.11.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 12
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 12
2.12 RECEIVER .................................................................................................................................................... 12
2.12.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 13
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 13
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 13
2.13 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................. 14
2.14 AUTO RTS HYSTERESIS ........................................................................................................................... 14
2.15 AUTO CTS FLOW CONTROL ..................................................................................................................... 14
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 15
2.16 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 16
TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 16
2.17 SPECIAL CHARACTER DETECT ............................................................................................................... 16
2.18 AUTO RS485 HALF-DUPLEX CONTROL .................................................................................................. 16
2.19 INFRARED MODE ........................................................................................................................................ 17
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 17
2.20 SLEEP MODE WITH AUTO WAKE-UP ...................................................................................................... 18
2.21 INTERNAL LOOPBACK .............................................................................................................................. 19
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 19
3.0 UART INTERNAL REGISTERS ........................................................................................................... 20
TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ...................................................................................... 20
TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1......................................... 21
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 22
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 22
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 22
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 22
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 23
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