XR16L2750_05 Datasheet, PDF (27/48 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

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REV. 1.2.1
XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION
TRIGGER FCTR FCTR FCR FCR FCR
TABLE BIT-5 BIT-4 BIT-7 BIT-6 BIT-5
Table-C 1
0
0
0
1
1
0
0
0
1
1
0
1
1
FCR
RECEIVE
BIT-4 TRIGGER LEVEL
0
1
0
1
8
16
56
60
TRANSMIT
TRIGGER
LEVEL
8
16
32
56
COMPATIBILITY
16C654
Table-D 1
1
X
X
X
X Programmable Programmable 16L2752, 16C2850,
via TRG
register.
via TRG
register.
16C2852, 16C850,
16C854, 16C864
FCTR[7] = 0. FCTR[7] = 1.
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
5 (default)
0
1
6
1
0
7
1
1
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2
WORD LENGTH
STOP BIT LENGTH
(BIT TIME(S))
0
5,6,7,8
1 (default)
1
5
1-1/2
1
6,7,8
2
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 11 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
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