XR16L2750_05 Datasheet, PDF (48/48 Pages) Exar Corporation – 2.25V TO 5.5V DUART WITH 64-BYTE FIFO

XR16L2750
2.25V TO 5.5V DUART WITH 64-BYTE FIFO
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REV. 1.2.1
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 23
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 24
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 24
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 24
TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 25
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 25
TABLE 10: TRANSMIT AND RECEIVE FIFO TRIGGER TABLE AND LEVEL SELECTION .......................................................................... 26
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 27
TABLE 11: PARITY SELECTION ........................................................................................................................................................ 28
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 28
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 29
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 30
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 31
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 31
TABLE 12: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 31
TABLE 13: AUTO RTS HYSTERESIS ................................................................................................................................................ 32
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY .......................................................................................... 32
4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 32
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 32
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 33
4.16 TRIGGER LEVEL REGISTER (TRG) - WRITE-ONLY ................................................................................. 33
4.17 RX/TX FIFO LEVEL COUNT REGISTER (FC) - READ-ONLY .................................................................... 33
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................ 33
TABLE 14: TRIGGER TABLE SELECT................................................................................................................................................ 33
4.19 ENHANCED FEATURE REGISTER (EFR) .................................................................................................. 34
TABLE 15: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 34
4.19.1 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ............................ 35
TABLE 16: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 36
ABSOLUTE MAXIMUM RATINGS...................................................................................37
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%) 37
ELECTRICAL CHARACTERISTICS ................................................................................37
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................37
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.25V to 5.5V .............................................. 37
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................38
Unless otherwise noted: TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc=2.25 - 5.5V, 70 pF load
where applicable........................................................................................................................................................ 38
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 39
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 39
FIGURE 17. DATA BUS WRITE TIMING............................................................................................................................................. 40
FIGURE 16. DATA BUS READ TIMING .............................................................................................................................................. 40
FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 41
FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 41
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 42
FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 42
FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B............................ 43
FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 43
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM) ....................................................................................44
PACKAGE DIMENSIONS (44 PIN PLCC) .........................................................................................................45
REVISION HISTORY.......................................................................................................................................46
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