XRT73L03 Datasheet, PDF (6/62 Pages) Exar Corporation – 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT

XRT73L03 3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.13
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PRELIMINARY
Figure 29. A channel in the XRT73L03 operating in the Analog Local Loop-Back Mode .............................. 46
COMMAND REGISTER CR4-(N) ....................................................................................................... 46
4.2 THE DIGITAL LOCAL LOOP-BACK MODE. .......................................................................................................... 47
Figure 30. The Digital Local Loop-Back path in a given channel of the XRT73L03 ........................................ 47
COMMAND REGISTER CR4-(N) ....................................................................................................... 47
4.3 THE REMOTE LOOP-BACK MODE ...................................................................................................................... 48
Figure 31. The Remote Loop-Back path in a given XRT73L03 Channel ........................................................ 48
COMMAND REGISTER CR4-(n) ....................................................................................................... 48
4.4 TXOFF FEATURES ........................................................................................................................................... 48
COMMAND REGISTER CR1-(N) ....................................................................................................... 49
TABLE 6: THE RELATIONSHIP BETWEEN THE TXOFF INPUT PIN, THE TXOFF BIT FIELD AND THE STATE OF THE TRANS-
MITTER ............................................................................................................................................... 49
4.5 THE TRANSMIT DRIVE MONITOR FEATURES ....................................................................................................... 49
Figure 32. The XRT73L03 employing the Transmit Drive Monitor Features ................................................... 50
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE ................................................................................................... 50
5.0 The Microprocessor Serial Interface .............................................................................................. 50
5.1 DESCRIPTION OF THE COMMAND REGISTERS ..................................................................................................... 50
COMMAND REGISTER CR1-(N) ....................................................................................................... 50
TABLE 7: ADDRESSES AND BIT FORMATS OF XRT73L03 COMMAND REGISTERS ................................................. 51
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ........................................................................... 52
5.2.1 Command Register - CR0-(n) ............................................................................................................ 52
COMMAND REGISTER CR0-(N) ........................................................................................................ 52
COMMAND REGISTER CR1-(N) ....................................................................................................... 52
5.2.3 Command Register CR2-(n) .............................................................................................................. 53
COMMAND REGISTER CR2-(N) ....................................................................................................... 53
COMMAND REGISTER CR3-(N) ....................................................................................................... 54
COMMAND REGISTER CR4-(N) ....................................................................................................... 54
TABLE 8: CONTENTS OF LLB(N) AND RLB(N) AND THE CORRESPONDING LOOP-BACK MODE FOR CHANNEL(N) .... 55
5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................................... 55
Figure 33. Microprocessor Serial Interface Data Structure ............................................................................. 56
Figure 34. Timing Diagram for the Microprocessor Serial Interface ................................................................ 57
ORDERING INFORMATION ............................................................................................. 58
PACKAGE DIMENSIONS ................................................................................................. 58
REVISION HISTORY ..................................................................................................................................... 59
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