XRT73L03 Datasheet, PDF (49/62 Pages) Exar Corporation – 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT

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PRELIMINARY
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT XRT73L03
REV. P1.0.13
4.0 DIAGNOSTIC FEATURES OF THE XRT73L03
The XRT73L03 supports equipment diagnostic activi-
ties by supporting the following Loop-Back modes in
each channel in the XRT73L03:
• Analog Local Loop-Back.
• Digital Local Loop-Back
• Remote Loop-Back
NOTE: In this data sheet we use the convention that Chan-
nel(n) refers to either channel 1, 2 or 3. Similarly, specific
input and output pins use this convention to denote which
channel it is associated with.
4.1 THE ANALOG LOCAL LOOP-BACK MODE
When a given channel in the XRT73L03 is configured
to operate in the Analog Local Loop-Back Mode, it ig-
nores any signals that are input to its RTIP(n) and
RRing(n) input pins. The Transmitting Terminal
Equipment transmits clock and data into this channel
via the TPData(n), TNData(n) and TxClk(n) input
pins. This data is processed through the Transmit
Clock Duty Cycle Adjust PLL and the HDB3/B3ZS
Encoder. Finally, this data outputs to the line via the
TTIP(n) and TRing(n) output pins. Additionally, this
data loops back into the Attenuator/Receive Equalizer
Block. Consequently, this data is processed through
the entire Receive Section of the channel. After this
post-Loop-Back data has been processed through
the Receive Section it outputs to the Near-End Re-
ceiving Terminal Equipment via the RPOS(n),
RNEG(n) and RxClk(n) output pins.
Figure 29 illustrates the path the data takes in a given
channel of the XRT73L03 when it is configured to op-
erate in the Analog Local Loop-Back Mode.
FIGURE 29. A CHANNEL IN THE XRT73L03 OPERATING IN THE ANALOG LOCAL LOOP-BACK MODE
RLOL(n) EXClk(n)
RTIP(n)
RRing(n)
AGC/
Equalizer
Slicer
Clock
Recovery
Invert
REQEN(n)
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
Peak
Detector
LOS Detector
Serial
Processor
Interface
Analog Local
Loop-Back Path
Data
Recovery
HDB3/
B3ZS
Decoder
Loop MUX
TTIP(n)
TRing(n)
TxLEV(n)
TxOFF(n)
DMO(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Device
Monitor
Transmit
Logic
Duty Cycle Adjust
Notes: 1. (n) = 1, 2 or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in
Hardware Mode.
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
MTIP(n)
MRing(n)
A given channel in the XRT73L03 can be configured
to operate in the Analog Local Loop-Back Mode by
employing either one of the following two steps:
NOTE: See Table 2 for a description of Command Registers
and Addresses for the different channels.
a. Operating in the HOST Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, write a "1" into the LLB(n) bit-
field and a "0" into the RLB(n) bit-field in Command
Register CR4.
COMMAND REGISTER CR4-(n)
D4
D3
D2
D1
D0
X STS-1/DS3_ Ch(n) E3_ Ch(n) LLB(n) RLB(n)
X
X
X
1
0
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