XRT73L03 Datasheet, PDF (26/62 Pages) Exar Corporation – 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT

XRT73L03 3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.13
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PRELIMINARY
SYSTEM DESCRIPTION
A functional block diagram of the XRT73L03 E3/DS3/
STS-1 Transceiver IC is presented in Figure 8. The
XRT73L03 contains three independent transmitter
and receiver sections and a common microprocessor
interface section.
THE TRANSMIT SECTION - CHANNELS 1, 2 AND 3
The Transmit Section of each Channel accepts TTL/
CMOS level signals from the Terminal Equipment in
either a Single-Rail or Dual-Rail format. The Transmit
Section takes this data and does the following:
• Encode this data into the B3ZS format if the DS3 or
SONET STS-1 Modes have been selected, or into
the HDB3 format if the E3 Mode has been selected.
• Convert the CMOS level B3ZS or HDB3 encoded
data into pulses with shapes that are compliant with
the various industry standard pulse template
requirements.
• Drive these pulses onto the line via the TTIP(n) and
TRing(n) output pins across a 1:1 Transformer.
NOTE: The Transmit Section drives a "1" (or a Mark) onto
the line by driving either a positive or negative polarity pulse
across the 1:1 Transformer in a given bit period. The Trans-
mit Section drives a "0" (or a Space) onto the line by driving
no pulse onto the line.
THE RECEIVE SECTION - CHANNELS 1, 2 AND 3
The Receive Section of each Channel receives a bi-
polar signal from the line via the RTIP and RRing sig-
nals across a 1:1 Transformer or a 0.01µF Capacitor.
The recovered clock and data outputs to the Local
Terminal Equipment in the form of CMOS level sig-
nals via the RPOS(n), RNEG(n) and RxClk(n) output
pins.
THE MICROPROCESSOR SERIAL INTERFACE
The XRT73L03 contains three identical channels.
The Microprocessor Interface Inputs are common to
all channels. The descriptions that follow refer to
Channel(n) where (n) represents Channel1,
Channel2 or Channel3.
The XRT73L03 can be configured to operate in either
the Hardware Mode or the HOST Mode.
a. Operating in the Hardware Mode
The XRT73L03 can be configured to operate in the
Hardware Mode by tying the HOST/(HW) input pin
(pin 8) to GND.
When the XRT73L03 is operating in the Hardware
Mode, the following is true:
1. The Microprocessor Serial Interface block is dis-
abled.
2. The XRT73L03 is configured via input pin set-
tings.
Each of the pins associated with the Microprocessor
Serial Interface takes on their alternative role as de-
fined in Table 1.
TABLE 1: ROLE OF MICROPROCESSOR SERIAL
INTERFACE PINS WHEN THE XRT73L03 IS OPERATING IN
THE HARDWARE MODE
PIN #
PIN NAME
61 CS/(ENDECDIS)
62
SClk/(RxOFF2)
63
SDI/(RxOFF1)
64
SDO/(E3_Ch1)
96 REGR/(RxClkINV)
FUNCTION WHILE IN
HARDWARE MODE
ENDECDIS
RxOFF2
RxOFF1
E3_Ch1
RxCKlkINV
When the XRT73L03 is operating in the Hardware
Mode, all of the remaining input pins become active.
b. Operating in the HOST Mode
The XRT73L03 can be configured to operate in the
HOST Mode by tying the HOST/(HW) input pin (pin 8)
to VDD.
When the XRT73L03 is operating in the HOST Mode,
the following is true:
1. The Microprocessor Serial Interface block is
enabled. Writing the appropriate data into the
on-chip Command Registers makes many config-
uration selections.
2. All of the following input pins are disabled and
should be connected to GND.
• Pins 8, 9 & 35 - TxLEV(n)
• Pins 6, 7 & 36 - TAOS(n)
• Pin 74, 82 & 100 - REQEN(n)
• Pin 69, 77 & 87 - RLB(n)
• Pin 68, 76 & 88 - LLB(n)
• Pin 92 & 102 - E3_Ch(n)
• Pin 65, 95 & 101 - STS1/DS3_Ch(n)
In HOST Mode Operation, the TxOFF(n) input pins
can still be used to turn on or turn off the Transmit
Output Drivers in Channels 1, 2 and 3, respectively.
The intent behind this feature is to permit a system
designed for redundancy to quickly switch out a de-
fective line card and switch-in the back-up line card.
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