XRT73L03 Datasheet, PDF (15/62 Pages) Exar Corporation – 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT

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PRELIMINARY
PIN DESCRIPTION
PIN #
85
SIGNAL NAME
RRing2
86
RxAVDD2
87
RLB2
88
LLB2
89
LOSTHR2
90
NC
91
NC
92
E3_Ch2
93
SR/(DR)
94
AGND3
95
STS1/DS3_Ch2
96
REGR/(RxClk-
INV)
97
EXDGND
3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT XRT73L03
REV. P1.0.13
TYPE
I
****
I
I
I
I
I
****
I
I
****
DESCRIPTION
Receive Ring Input - Channel 2:
Refer to the description of pin 71, RRing 1
Receive Analog 3.3V+ 5% VDD - Channel 2
Remote Loop-back - Channel 2:
Refer to the description of pin 69, RLB1
Local Loop-back - Channel 2:
Refer to the description of pin 68, LLB1
Loss of Signal Threshold Control - Channel 2:
Refer to the description of pin 67, LOSTHR1
No Connection
No Connection
E3 Select Input - Channel 2:
A "High" on this pin configures Channel 2 of the XRT73L03 to operate in the
E3 Mode.
A "Low" on this pin configures Channel 2 of the XRT73L03 to check the state
of the STS-1/DS3_Ch2 input pin
NOTE: This input pin is ignored and should be connected to GND if the
XRT73L03 is operating in the HOST Mode.
Receive Output Single-Rail/Dual-Rail Select:
Setting this pin "High" configures the Receive Sections of all Channels to out-
put data in a Single-Rail Mode to the Terminal Equipment.
Setting this pin "Low" configures the Receive Section of all Channels to output
data in a Dual-Rail Mode to the Terminal Equipment.
Analog Ground (Substrate Connection) - Channel 3
STS-1/DS3 Select Input - Channel 2:
Refer to the description of pin 65, STS1/DS3_Ch1
Register Reset Input pin (Invert RxClk(n)) Output - Select):
The function of this pin depends upon whether the XRT73L03 is operating in
the HOST Mode or in the Hardware Mode.
NOTE: This pin is internally pulled "High".
In the HOST-Mode - Register Reset Input pin:
Setting this input pin "Low" causes the XRT73L03 to reset the contents of the
Command Registers to their default settings and default operating configura-
tion.
In the Hardware Mode - Invert RxClk Output Select:
Setting this input pin "High" configures the Receive Section of all Channels in
the XRT73L03 to invert their RxClk(n) clock output signals and configures
Channel (n) to output the recovered data via the RPOS(n) and RNEG(n) out-
put pins on the falling edge of RxClk(n).
Setting this pin "Low" configures Channel (n) to output the recovered data via
the RPOS(n) and RNEG(n) output pins on the rising edge of RxClk(n).
External Reference Clock GND
12