XRT73L03 Datasheet, PDF (46/62 Pages) Exar Corporation – 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT

XRT73L03 3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.13
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PRELIMINARY
FIGURE 25. HOW THE XRT73L03 OUTPUTS DATA ON THE RPOS AND RNEG OUTPUT PINS
RPOS
RNEG
RxClk
RxClk(n) is the Recovered Clock signal from the in-
coming Received line signal. As a result, these clock
signals are typically 34.368 MHz for E3 applications,
44.736 MHz for DS3 applications and 51.84 MHz for
SONET STS-1 applications.
In general, if a given channel received a positive-po-
larity pulse in the incoming line signal via the RTIP(n)
and RRing(n) input pins, then the channel pulses its
corresponding RPOS(n) output pin "High". Con-
versely, if the channel received a negative-polarity
pulse in the incoming line signal via the RTIP(n) and
RRing(n) input pins, then the Channel(n) pulses its
corresponding RNEG(n) output pin "High".
Inverting the RxClk(n) outputs
Each channel can invert the RxClk(n) signals with re-
spect to the delivery of the RPOS(n) and RNEG(n)
output data to the Receiving Terminal Equipment.
This feature may be useful for those customers
whose Receiving Terminal Equipment is designed
such that the RPOS(n) and RNEG(n) data must be
sampled on the rising edge of RxClk(n). Figure 26 il-
lustrates the behavior of the RPOS(n), RNEG(n) and
RxClk(n) signals when the RxClk(n) signal has been
inverted.
a. Operating in the Hardware Mode
Setting the RxClkINV pin (pin 62) “High” results in all
channels of the XRT73L03 to output the recovered
data on RPOS(n) and RNEG(n) on the falling edge of
RxClk(n). Setting this pin “Low” results in the recov-
ered data on RPOS(n) and RNEG(n) to output on the
rising edge of RxClk(n).
FIGURE 26. THE BEHAVIOR OF THE RPOS, RNEG AND RXCLK SIGNALS WHEN RXCLK IS INVERTED
RPOS
RNEG
RxClk
b. Operating in the HOST Mode
In order to configure a channel of the XRT73L03 to in-
vert the RxClk(n) output signal, the XRT73L03 must
be operating in the HOST Mode.
To invert RxClk(n) associated with Channel(n), write a
"1" into the RxClk(n)INV bit-field in Command Regis-
ter CR-3 as illustrated below.
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