XRT73L03 Datasheet, PDF (50/62 Pages) Exar Corporation – 3 CHANNEL E3/DS3/STS-1 LINE INTERFCE UNIT

XRT73L03 3 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. P1.0.13
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PRELIMINARY
b. Operating in the Hardware Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, set the LLB(n) input pin (pin 34,
54 or 42) “High" and the RLB(n) input pin (pin 35, 53
or 43) “Low".
4.2 THE DIGITAL LOCAL LOOP-BACK MODE.
When a given channel in the XRT73L03 is configured
to operate in the Digital Local Loop-Back Mode, the
channel ignores any signals that are input to the RTIP
and RRing input pins. The Transmitting Terminal
Equipment transmits clock and data into the
XRT73L03 via the TPData, TNData and TxClk input
pins. This data is processed through the Transmit
Clock Duty Cycle Adjust PLL and the HDB3/B3ZS
Encoder block. At this point, this data loops back to
the HDB3/B3ZS Decoder block. After this post-Loop-
Back data has been processed through the HDB3/
B3ZS Decoder block, it outputs to the Near-End Re-
ceiving Terminal Equipment via the RPOS, RNEG
and RxClk output pins.
Figure 30 illustrates the path the data takes in the
XRT73L03 when the chip is configured to operate in
the Digital Local Loop-Back Mode.
FIGURE 30. THE DIGITAL LOCAL LOOP-BACK PATH IN A GIVEN CHANNEL OF THE XRT73L03
RLOL(n) EXClk(n)
RTIP(n)
RRing(n)
REQEN(n
)
LOSTHR(n)
SDI
SDO
SClk
CS
REGR
TTIP(n)
TRing(n)
TxLEV(n)
TxOFF(n)
DMO(n)
AGC/
Equalizer
Slicer
Clock
Recovery
Peak
Detector
LOS Detector
Serial
Processor
Interface
Digital Local
Loop-Back Path
Data
Recovery
Loop MUX
Invert
HDB3/
B3ZS
Decoder
Pulse
Shaping
HDB3/
B3ZS
Encoder
Device
Monitor
Transmit
Logic
Duty Cycle Adjust
RxClk(n)
RPOS(n)
RNEG(n)
LCV(n)
ENDECDIS
RLOS(n)
LLB(n)
RLB(n)
TAOS(n)
TPData(n)
TNData(n)
TxClk(n)
MTIP(n)
MRing(n)
Notes: 1. (n) = 1, 2 or 3 for respective Channels
To configure a channel to operate in the Digital Local
Loop-Back Mode, employ either one of the following
two-steps:
a. Operating in the HOST Mode
To configure Channel (n), write a “1" into both the
LLB and RLB bit-fields in Command Register CR4-
(n), as illustrated below.
COMMAND REGISTER CR4-(N)
D4
D3
D2
D1
D0
X STS-1/DS3_Ch(n) E3_Ch(n) LLB(n) RLB(n)
X
X
X
1
1
b. Operating in the Hardware Mode
To configure Channel (n), pull both the LLB input pin
(pin 34, 54 or 42) and the RLB input pin (pin 35, 53 or
43) “High".
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