XR16L784_08 Datasheet, PDF (6/51 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART

XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
REV. 1.2.3
1.0 DESCRIPTION
The XR16L784 (784) integrates the functions of 4 enhanced 16550 UARTs, a general purpose 16-bit timer/
counter and an on-chip oscillator. The device configuration registers include a set of four consecutive interrupt
source registers that provides interrupt-status for all 4 UARTs, timer/counter and a sleep wake up indicator.
Each UART channel has its own 16550 UART compatible configuration register set for individual channel
control, status, and data transfer. Additionally, each UART channel has 64-byte of transmit and receive FIFOs,
automatic RTS/CTS or DTR/DSR hardware flow control with hysteresis control, automatic Xon/Xoff and
special character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level
counters, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of
divide by 1 or 4, and data rate up to 6.25 Mbps with 8X sampling clock rate or 3.125Mbps in the 16X rate. The
XR16L784 is a 5V and 3.3V device with 5 volt tolerant inputs (except XTAL1).
2.0 FUNCTIONAL DESCRIPTIONS
2.1 Device Reset
2.1.1 Hardware Reset
The RST# input resets the internal registers and the serial interface outputs in all 4 channels to their default
state (see Table 19). A LOW pulse of longer than 40 ns duration will be required to activate the reset function
in the device.
2.1.2 Software Reset
The internal registers of each UART can be reset by writing to the RESET register in the Device Configuration
Registers. For more details, see the RESET register description on page 23.
2.2 UART Channel Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on the chip select pins, CS#, allows the user to
select one of the UART channels to configure, send transmit data and/or unload receive data to/from the
UART. When address line A7 = 0, address lines A5:A4 are used to select one of the eight channels. See
Table 1 below for UART channel selection.
TABLE 1: UART CHANNEL SELECTION
A7
A6
A5
A4
FUNCTION
0
0
0
0
Channel 0 Selected
0
0
0
1
Channel 1 Selected
0
0
1
0
Channel 2 Selected
0
0
1
1
Channel 3 Selected
0
1
X
X
Reserved
2.3 Simultaneous Write to All Channels
During a write cycle, the setting of REGB bit-0 to a logic 1 will override the channel selection of address A5:A4
and allow a simultaneous write to all 4 UART channels when any channel is written to. This functional
capability allow the registers in all 8 UART channels to be modified concurrently, saving individual channel
initialization time. Caution should be considered, however, when using this capability. Any in-process serial
data transfer may be disrupted by changing an active channel’s mode. Also, REGB bit-0 should be reset to a
logic 0 before attempting to read from the UART.
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