XR16L784_08 Datasheet, PDF (22/51 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART

XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
REV. 1.2.3
TABLE 9: UART CHANNEL [3:0] INTERRUPT SOURCE ENCODING AND CLEARING
PRIORITY BIT2 BIT1 BIT0
INTERRUPT SOURCE(S) AND CLEARING
x
0 0 0 None
1
0 0 1 RXRDY & RX Line Status (logic OR of LSR[4:1]). RXRDY INT clears by reading data in the
RX FIFO until it falls below the trigger level; RX Line Status INT cleared after reading LSR
register.
2
0 1 0 RXRDY Time-out: Cleared when the FIFO becomes empty.
3
0 1 1 TXRDY, THR or TSR (auto RS485 mode) empty, clears after reading ISR register.
4
1 0 0 MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon or special character detected. The first two
clear after reading MSR register; Xoff/Xon or special char. detect INT clears after reading
ISR register.
5
1 0 1 Reserved.
6
1 1 0 Reserved.
7
1 1 1 TIMER Time-out, shows up as a channel 0 INT. It clears after reading the TIMERCNTL regis-
ter. Reserved in other channels.
3.1.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (DEFAULT
0XXX-XX-00-00)
A 16-bit down-count timer for general purpose timer or counter. Its clock source may be selected from internal
crystal oscillator or externally on pin TMRCK. The timer can be set to be a single-shot for a one-time event or
re-triggerable for a periodic event. An interrupt may be generated in the INT Register when the timer times out.
It is controlled through 4 configuration registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. These
registers provide start/stop and re-triggerable or one-shot operation. The time-out output of the Timer can be
set to generate an interrupt for system or event alarm.
FIGURE 15. TIMER/COUNTER CIRCUIT.
TIMERMSB and TIMERLSB
(16-bit Value)
TMRCK
1
OSC. CLOCK
0
16-Bit
Time-out
1
Timer/Counter
0
Clock
TIMERCNTL [3] ^Select
Start/Stop
TIMERCNTL [1]
TIMERCNTL [2] ^{Single/Re-triggerable}
Re-trigger
0
1
Single-shot
TIMERCNTL [0] ^{Timer Interrupt Enable}
Timer Interrupt, Ch-0 INT=7
No Interrupt
TABLE 10: TIMER CONTROL REGISTER
TIMERCNTL [0] Logic 0 (default) disables Timer-Counter interrupt and logic one enables the interrupt, reading the
TIMERCNTL clears the interrupt.
TIMERCNLT [1] Logic 0 (default) stops/pauses the timer and logic one starts/re-starts the timer/counter.
TIMERCNTL [2] Logic0 (default) selects re-trigger timer function and logic one selects one-shot (timer function.
TIMERCNTL [3] Logic 0 (default) selects internal and logic one selects external clock to the timer/counter.
TIMERCNTL [7:4] Reserved (defaults to zero).
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