XR16L784_08 Datasheet, PDF (38/51 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART

XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
REV. 1.2.3
4.13 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
TABLE 18: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3
0
0
1
0
1
X
X
X
1
0
1
0
EFR BIT-2
CONT-2
0
0
0
1
1
X
X
X
0
1
1
0
EFR BIT-1
CONT-1
0
X
X
X
X
0
1
0
1
1
1
1
EFR BIT-0
CONT-0
TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0
No TX and RX flow control (default and reset)
X
No transmit flow control
X
Transmit Xon1/Xoff1
X
Transmit Xon2/Xoff2
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
0
No receive flow control
0
Receiver compares Xon1/Xoff1
1
Receiver compares Xon2/Xoff2
1
Transmit Xon1/ Xoff1,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
Transmit Xon2/Xoff2,
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1
No transmit flow control,
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
EFR[3:0]: Software Flow Control Select
Combinations of software flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with ST16C554 mode (default).
• Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are
enabled.
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