XR16L784_08 Datasheet, PDF (13/51 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART

XR16L784
REV. 1.2.3
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
2.10.1 Auto CTS/DSR Flow Control
Automatic CTS/DSR flow control is used to prevent data overrun to the remote receiver FIFO. The CTS/DSR
pin is monitored to suspend/restart local transmitter. The flow control features are individually selected to fit
specific application requirement (see Figure 10):
• Select CTS (and RTS) or DSR (and DTR) through MCR bit-2.
• Enable auto CTS/DSR flow control using EFR bit-7.
With the Auto CTS or Auto DTR function enabled, the UART will suspend transmission as soon as the stop bit
of the character in the Transmit Shift Register has been shifted out. Transmission is resumed after the CTS#/
DTR# input is re-asserted (logic 0), indicating more data may be sent.
• If used, enable CTS/DSR interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt
when the CTS#/DSR# pin makes a transition: ISR bit-5 will be set to a logic 1, and UART will suspend TX
transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed
after the CTS#/DSR# input returns LOW, indicating more data may be sent.
FIGURE 10. AUTO RTS/DTR AND CTS/DSR FLOW CONTROL OPERATION
Local UART
UARTA
Receiver FIFO
Trigger Reached
RXA
TXB
Remote UART
UARTB
Transmitter
Auto RTS
Trigger Level
Transmitter
RTSA#
TXA
CTSB#
RXB
Auto CTS
Monitor
Receiver FIFO
Trigger Reached
Auto CTS
Monitor
CTSA#
RTSB#
Auto RTS
Trigger Level
RTSA#
CTSB#
TXB
Assert RTS# to Begin
Transmission
1
ON
2
7
ON
3
OFF
8 ^OFF
10 ON
11
ON
Data Starts
4
6 _Suspend ^Restart
9
RXA FIFO
Receive
INTA
Data
RX FIFO
Trigger Level
5
(RXA FIFO
Interrupt)
RTS High
Threshold
RTS Low
Threshold
RX FIFO
12 _{Trigger Level}
RTSCTS1
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
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