XR16L784_08 Datasheet, PDF (37/51 Pages) Exar Corporation – HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART

REV. 1.2.3
XR16L784
HIGH PERFORMANCE 2.97V TO 5.5V QUAD UART
TABLE 17: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT-3
FCTR BIT-2
FCTR BIT-1
FCTR BIT-0
RTS/DTR HYSTERESIS
(CHARACTERS)
0
0
0
0
0
0
0
0
1
+/- 4
0
0
1
0
+/- 6
0
0
1
1
+/- 8
0
1
0
0
+/- 8
0
1
0
1
+/- 16
0
1
1
0
+/- 24
0
1
1
1
+/- 32
1
1
0
0
+/- 12
1
1
0
1
+/- 20
1
1
1
0
+/- 28
1
1
1
1
+/- 36
1
0
0
0
+/- 40
1
0
0
1
+/- 44
1
0
1
0
+/- 48
1
0
1
1
+/- 52
FCTR[4]: Infrared RX Input Logic Select
• Logic 0 = Select RX input as active high encoded IrDA data, normal, (default).
• Logic 1 = Select RX input as active low encoded IrDA data, inverted.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
• Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
• Logic 1 = Enable Auto RS485 half duplex direction control. RTS# output changes its logic level from HIGH to
LOW when finished sending the last stop bit of the last character out of the TSR register. It changes from
LOW to HIGH when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior
sending the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register
(TSR) empty.
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trigger level table A, B, C or D. When table A, B, or C is
selected the auto RTS flow control trigger level is set to "next FIFO trigger level" for compatibility to ST16C550
and ST16C650 series. RTS/DTR# triggers on the next level of the RX FIFO trigger level, in another word, one
FIFO level above and one FIFO level below. See in Table 14 for complete selection with FCR bit 4-5 and FCTR
bit 6-7, i.e. if Table C is used on the receiver with RX FIFO trigger level set to 56 bytes, RTS/DTR# output will
de-assert at 60 and re-assert at 16.
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